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| exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com ? ? ? ? XRT7302 2 channel e3/ds3/sts-1 line interface unit august 2000 rev. 1.1.5 general description the XRT7302 dual channel e3/ds3/sts-1 trans- ceiver ic consists of two fully integrated transmitter and receiver line transceivers designed for e3, ds3 or sonet sts-1 applications. each channel within the XRT7302 can be configured to support the e3 (34.368 mbps), ds3 (44.736 mbps) or the sonet sts-1 (51.84 mbps) rates. each chan- nel can be configured to operate in a mode/data rate that is independent of the other channel. in the transmit direction, each channel within the XRT7302 will encode input data to either b3zs or hdb3 format and convert the data into the appropri- ate pulse shapes for transmission over coaxial cable via a 1:1 transformer. in the receive direction, the XRT7302 can perform equalization on incoming signals, perform clock re- covery, decode data from either b3zs or hdb3 for- mat, convert the receive data into ttl/cmos format, check for los or lol conditions and detect and de- clare the occurrence of line code violations. applications ? digital cross connect systems ? csu/dsu equipment ? routers ? fiber optic terminals ? multiplexers ? atm switches features ? meets e3/ds3/sts-1 jitter tolerance require- ments ? contains a 4-wire microprocessor serial interface ? full loop-back capability ? transmit and receive power down modes ? full redundancy support ? single +5v power supply ? uses minimum external components ? operates over -40c to +85c temperature range ? available in an 80 pin tqfp thermal enhanced package with integral heat sink XRT7302 block diagram agc/ equalizer serial processor interface peak detector los detector pulse shaping hdb3/ b3zs encoder transmit logic duty cycle adjust slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder sdi sdo sclk cs regr ttip(n) tring(n) rtip(n) rring(n) reqen(n) rxclk(n) rpos(n) rneg(n) lcv(n) rlos(n) llb(n) rlb(n) taos(n) tpdata(n) tndata(n) txclk(n) e3_ch(n) sts-1/ds3_ch(n) host/hw rlol(n) exclk(n) rxclkinv channel 1 channel 2 device monitor tx control txlev(n) txoff(n) dmo(n) mtip(n) mring(n) endecdis notes: 1. (n) = 1 or 2 for the respective channel. 2. serial processor interface pins are shared by both channels in host mode and are redefined in hardware mode. losthr(n) rxoff(n)
XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 2 transmit interface characteristics ? accepts either single rail or dual rail data from terminal equipment, and generates a bipolar signal ? integrated pulse shaping circuit ? built-in b3zs/hdb3 encoder (which can be dis- abled) ? contains "transmit clock duty cycle correction" circuit on-chip ? generates pulses that comply with the itu-t g.703 pulse template (e3 applications) ? generates pulses that comply with the dsx-3 pulse template, as specified in bellcore gr-499 -core and ansi t1.102_1993 ? generates pulses that comply with the stsx-1 pulse template, as specified in bellcore gr-253- core ? transmitter can be turned off in order to support "redundancy designs" receive interface characteristics ? integrated adaptive receive equalization (optional) and timing recovery ? declares and clears the los alarm per itu-t g.775 requirements (e3 and ds3 applications) ? meets jitter tolerance requirements, as specified in itu-t g.823_1993 (for e3 applications) ? meets jitter tolerance requirements, as specified in bellcore gr-499-core (for ds3 applications) ? declares loss of signal (los) and loss of lock (lol) alarms ? built-in b3zs/hdb3 decoder (which can be dis- abled) ? recovered data can be automatically muted while the los condition is declared ? outputs either single rail or dual rail data to the terminal equipment ? receiver can be powered down in order to con- serve power in "redundancy designs" pin out of the XRT7302 txlev1 taos1 dvdd dmo1 dgnd agnd dvdd host/(hw) rxclk1 rneg1 rpos1 dgnd rlos1 lcv1 rlol1 exclk1 cs/(endecdis) sclk/(rxoff2) sdi/(rxoff1) sdo/(e3_ch1) sts-1/ds3_ch1 ict losthr1 llb1 rlb1 avdd rring1 rtip1 agnd reqen1 reqen2 agnd rtip2 rring2 avdd rlb2 llb2 losthr2 e3_ch2 sr/dr txlev2 taos2 dvdd dmo2 dgnd agnd dvdd losmuten rxclk2 rneg2 rpos2 dgnd rlos2 lcv2 rlol2 exclk2 vdd gnd regr/(rxclkinv) sts-1/ds3_ch2 80 lead tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 txoff1 txclk1 tpdata1 tndata1 mtip1 mring1 avdd ttip1 tring1 agnd agnd tring2 ttip2 avdd mring2 mtip2 tndata2 tpdata2 txclk2 txoff2 ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 i table of contents general description ........................................................................................................... 1 applications .................................................................................................................. ....................... 1 features ...................................................................................................................... .......................... 1 XRT7302 block diagram ......................................................................................................... ............ 1 transmit interface characteristics ........................................................................................ 2 receive interface characteristics ........................................................................................... 2 pin out of the XRT7302 ........................................................................................................ .............. 2 table of contents i pin descriptions .............................................................................................................. ... 3 electrical characteristics ................................................................................. 18 absolute maximum ratings ................................................................................................... 1 8 figure 1.transmit pulse amplitude test circuit for e3, ds3 and sts-1 rates (typical channel shown) ...... 20 figure 2.timing diagram of the transmit terminal input interface .............................................................. .. 20 figure 3.timing diagram of the receive terminal output interface .............................................................. 20 figure 4.microprocessor serial interface data structure ....................................................................... ........ 24 figure 5.timing diagram for the microprocessor serial interface ............................................................... ... 25 system description ................................................................................................... 26 the transmit section (channels 1 and 2) ................................................................................ 26 the receive section (channels 1 and 2) ................................................................................... 26 the microprocessor serial interface ................................................................................... 26 the hardware mode ............................................................................................................. ........... 26 the host mode ................................................................................................................. .................. 26 table 1:role of microprocessor serial interface pins when the XRT7302 is operating in the "hardware" mode. 26 figure 6.functional block diagram of the XRT7302 .............................................................................. ........ 27 1.0 selecting the data rate ................................................................................................... ...... 27 1.1 c onfiguring c hannel 1 ............................................................................................................. 27 table 2:selecting the data rate for channel 1, (within the XRT7302), via the "e3_ch1" and "sts-1/ds3_ch1" input pins (hardware mode) .................................................................................................... .......... 28 command register, cr4 (address = 0x04) ......................................................................... 28 table 3:selecting the data rate for channel 1 (within the XRT7302); via the "sts-1/ds3_ch1" and the "e3_ch1" bit-fields, within command register cr4 (host mode) ..................................................... 28 1.2 c onfiguring c hannel 2 ............................................................................................................. 28 table 4:selecting the data rate for channel 2 (within the XRT7302) via the "e3_ch2" and "sts-1/ds3_ch2" input pins (hardware mode) .................................................................................................... .......... 28 command register, cr12 (address = 0x0c) ...................................................................... 29 table 5:selecting the data rate for channel 2 (within the XRT7302) via the "e3_ch2" and "sts-1/ds3_ch2" bit fields, within command register cr4 (host mode) .................................................................... 29 2.0 the transmit section ...................................................................................................... ......... 29 2.1 t he t ransmit l ogic b lock ......................................................................................................... 29 accepting "dual-rail" data from the terminal equipment ................................................................. 29 figure 7. illustration of the typical interface for the transmission of data in a dual rail format, from the "trans- mitting" terminal equipment to the "transmit section" of a channel within the XRT7302 ............... 30 figure 8.illustration on how the XRT7302 samples the data on the tpdata and tndata input pins ............ 30 XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 ii accepting "single-rail" data from the terminal equipment .............................................................. 30 command register 1 (address = 0x01) ............................................................................... 31 command register 9 (address = 0x09) ............................................................................... 31 figure 9.illustration of the behavior of the tpdata and txclk input sgnals, while the transmit logic block is accepting single-rail data from the terminal equipment ................................................................ 31 2.2 t he t ransmit c lock d uty c ycle a djust c ircuitry ................................................................. 31 2.3 t he hdb3/b3zs e ncoder b lock ............................................................................................... 32 b3zs encoding ................................................................................................................. ................. 32 figure 10.an example of b3zs encoding ......................................................................................... ............. 32 hdb3 encoding ................................................................................................................. ................. 32 figure 11.an example of hdb3 encoding ......................................................................................... ............. 33 disabling the "hdb3/b3zs" encoder ............................................................................................. .... 33 command register, cr2 (address = 0x02) ......................................................................... 33 command register, cr10 (address = 0x0a) ....................................................................... 33 2.4 t he t ransmit p ulse s haping c ircuitry .................................................................................... 33 figure 12.the "bellcore gr-499-core" transmit output pulse template for ds3 applications .................. 34 figure 13.the "bellcore gr-253-core" transmit output pulse template for sonet sts-1 applications . 35 enabling the transmit line build-out circuit .................................................................................. ... 35 command register, cr1 (address = 0x01) ......................................................................... 35 disabling the transmit line build-out circuit ................................................................................. ... 36 design guideline for setting the transmit line build-out circuit ...................................................... 36 command register, cr9 (address = 0x09) ......................................................................... 36 command register, cr1 (address = 0x01) ......................................................................... 36 command register, cr9 (address = 0x09) ......................................................................... 36 the transmit line build-out circuit and e3 applications .................................................................. 36 2.5 i nterfacing the t ransmit s ections of the XRT7302 to the l ine ........................................... 36 figure 14.recommended schematic for interfacing the transmit section of the XRT7302 to the line ......... 37 transformer vendor information ........................................................................................... 37 3.0 the receive section ....................................................................................................... ............ 38 3.1 i nterfacing the r eceive s ections of the XRT7302 to the l ine ............................................. 38 figure 15.recommended schematic for interfacing the receive section of the XRT7302 to the line (transform- er-coupling) .................................................................................................................. .................... 38 transformer vendor information ........................................................................................... 39 figure 16.recommended schematic for interfacing the receive section of the XRT7302 to the line (capaci- tive-coupling) - (typical channel shown) ...................................................................................... ..... 39 figure 17.illustration of the typical application for the system installer .................................................... ..... 40 3.2 t he r eceive e qualizer b lock .................................................................................................... 40 command register cr2 (address = 0x02) .......................................................................... 41 command register cr10 (address = 0x0a) ........................................................................ 41 3.3 p eak d etector and s licer ......................................................................................................... 41 3.4 c lock r ecovery pll .................................................................................................................. 41 3.5 t he hdb3/b3zs d ecoder .......................................................................................................... 42 b3zs decoding (ds3/sts-1 applications) ........................................................................................ 42 figure 18.an example of b3zs decoding ......................................................................................... ............. 42 hdb3 decoding (e3 applications) ............................................................................................... ...... 42 ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 iii figure 19.an example of hdb3 decoding ......................................................................................... ............ 43 configuring the hdb3/b3zs decoder ............................................................................................. .. 43 command register cr2 (address = 0x02) .......................................................................... 43 command register cr10 (address = 0x0a) ....................................................................... 43 3.6 los d eclaration /c learance .................................................................................................... 43 the los declaration/clearance criteria for e3 applications ............................................................ 44 figure 20.illustration of the signal levels that the XRT7302 will declare and clear los ............................... 44 figure 21.the behavior the los output indicator, in response to the loss of signal, and the restoration of sig- nal ........................................................................................................................... .......................... 45 the los declaration/clearance criteria for ds3 and sts-1 applications ....................................... 45 table 6:the alos (analog los) declaration and clearance thresholds for a given setting of losthr and reqen (ds3 and sts-1 applications) ............................................................................................ . 45 command register 0, (address = 0x00) .............................................................................. 46 command register 8, (address = 0x08) .............................................................................. 46 command register cr2 (address = 0x02) .......................................................................... 46 command register cr10 (address = 0x0a) ....................................................................... 46 command register cr0, (address = 0x00) ......................................................................... 47 command register cr8, (address = 0x08) ......................................................................... 47 command register cr2 (address = 0x02 ........................................................................... 47 command register cr10 (address = 0x0a ......................................................................... 47 muting the recovered data while the los is being declared ........................................................... 47 command register cr3 (address = 0x03) .......................................................................... 48 command register cr11 (address = 0x0b) ....................................................................... 48 3.7 r outing the r ecovered t iming and d ata i nformation to the "r eceiving t erminal e quipment " ............................................................................................................................... .............................. 48 routing "dual-rail" format data to the receiving terminal equipment ........................................... 48 figure 22.illustration of the typical interface for the transmission of data in a dual-rail format, from the "re- ceive section" of the XRT7302" to the receiving terminal equipment ........................................... 49 figure 23.illustration on how the XRT7302 outputs data on the rpos and rneg output pins .................... 49 figure 24.illustration of the behavior of the rpos, rneg, and rxclk(n) signals, when rxclk(n) is inverted 50 routing single-rail format (binary data stream) data to the receive terminal equipment ........... 50 command register cr3 (address = 0x03) .......................................................................... 50 command register cr11 (address = 0x0b) ....................................................................... 50 command register cr3 (address = 0x03) .......................................................................... 50 command register 11 (address = 0x0b) ............................................................................. 50 figure 25.illustration of the typical interface for the transmission of data in a single-rail format, from the re- ceive section of the XRT7302 to the receiving terminal equipment .............................................. 51 figure 26.illustration of the behavior of the rpos and rxclk output signals, while the XRT7302 is transmitting "single-rail" data to the receiving terminal equipment ................................................................. 51 3.8 s hutting off the r eceive s ection .......................................................................................... 51 command register cr3 (address = 0x03) .......................................................................... 52 command register cr11 (address = 0x0b) ....................................................................... 52 4.0 diagnostic features of the XRT7302 .................................................................................. 53 4.1 t he a nalog l ocal l oop - back m ode ......................................................................................... 53 XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 iv figure 27.illustration of a typical channel(n) (within the XRT7302) operating in the analog local loop-back mode .......................................................................................................................... ....................... 53 4.2 t he d igital l ocal l oop - back m ode . .......................................................................................... 54 figure 28.illustration of the "digital local loop-back" path in a typical channel(n) (of the XRT7302) .......... 54 command register cr4 (address = 0x04) .......................................................................... 55 command register cr12 (address = 0x0c) ........................................................................ 55 4.3 t he r emote l oop - back m ode .................................................................................................... 55 figure 29.illustration of the "remote loop-back" path, within a typical channel(n) (of the XRT7302) .......... 56 command register cr4 (address = 0x04) .......................................................................... 56 command register cr12 (address = 0x0c) ........................................................................ 56 4.4 t x off f eatures ......................................................................................................................... 56 command register cr1 (address = 0x01) .......................................................................... 57 command register cr9 (address = 0x09) .......................................................................... 57 table 7:the relationship between the txoff input pin, the txoff bit field and the state of the transmitter ............................................................................................................................... ..............................57 4.5 t he t ransmit d rive m onitor f eatures .................................................................................... 57 figure 30.illustration of a typical channel of the XRT7302 employing the transmit drive monitor features 58 4.6 t he taos (t ransmit a ll o ne s) f eature .................................................................................. 58 command register cr1 (address = 0x01) .......................................................................... 58 5.0 the microprocessor serial interface ............................................................................. 59 command register cr9 (address = 0x09) .......................................................................... 59 5.1 d escription of the c ommand r egisters .................................................................................. 59 table 8:addresses and bit formats of XRT7302 command registers .......................................................... 60 command register - cr0 ........................................................................................................ .......... 60 command register cr0, (address = 0x00) ......................................................................... 60 command register cr1 (address = 0x01) .......................................................................... 61 command register cr2 .......................................................................................................... .......... 62 command register cr2 (address = 0x02) .......................................................................... 62 command register cr3 (address = 0x03) .......................................................................... 63 command register cr4 (address = 0x04) .......................................................................... 63 table 9:contents of "llb1" and "rlb1" and the corresponding loop-back mode for channel 1 ................. 64 command register - cr8 ........................................................................................................ .......... 64 command register 8, (address = 0x08) .............................................................................. 64 command register cr9 .......................................................................................................... .......... 64 command register cr9 (address = 0x09) .......................................................................... 65 command register cr10 ......................................................................................................... ......... 65 command register cr10 (address = 0x0a) ........................................................................ 65 5.2 c ommand r egister cr11 ........................................................................................................... 66 command register cr11 (address = 0x0b) ........................................................................ 66 command register cr12 ......................................................................................................... ......... 67 command register cr 12 (address = 0x0c) ....................................................................... 67 table 10:contents of "llb2" and "rlb2" and the corresponding loop-back mode for channel 2 ............... 67 ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 v 5.3 o perating the m icroprocessor s erial i nterface . ................................................................. 67 figure 31.microprocessor serial interface data structure ...................................................................... ....... 68 figure 32.timing diagram for the microprocessor serial interface .............................................................. .. 69 ordering information ....................................................................................................... 70 package dimensions ....................................................................................................... 70 revision history .............................................................................................................. ................. 71 XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 3 pin descriptions pin description p in #s ignal n ame t ype d escription 1 txlev1 i transmit line build-out enable/disable select - channel 1: this input pin permits the user to enable or disable the transmit line build-out circuit, within channel 1 of the XRT7302. setting this pin to "high" disables the line build-out circuit within channel 1. in this mode, channel 1 will output unshaped (e.g., square-wave) pulses onto the line via the ttip1 and tring1 output pins. setting this pin to "low" enables the line build-out circuit within channel 1. in this mode, channel 1 will output shaped pulses onto the line via the ttip1 and tring1 output pins. in order to comply with the "isolated dsx-3/stsx-1 pulse template require- ments (per bellcore gr-499-core or bellcore gr-253-core), the user should: 1. set this input pin to "1", if the cable length (between the cross-connect and the transmit output of channel 1) is greater than 225 feet. 2. set this input pin to "0", if the cable length (between the cross-connect and the transmit output of channel 1) is less than 225 feet. this pin is active only if the following two conditions are true: a. the XRT7302 is configured to operate in either the ds3 or sonet sts-1 modes. b. the XRT7302 is configured to operate in the "hardware" mode. n ote : note: the user should tie this pin to gnd if the XRT7302 is going to be operating in the "host" mode 2 ta o s 1 i transmit all ones select - channel 1: a "high" on this pin causes the transmit section, within channel 1 to generate and transmit a continuous ami "all 1s" pattern onto the line. the frequency of this "1s" pattern is determined by txclk. n otes : 1. this input pin is ignored if the XRT7302 is operating in the "host" mode. 2. the user should tie this pin to gnd, if the XRT7302 is going to be operating in the "host" mode. 3 dvdd **** transmit digital vdd (for transmitter 1) 4 dmo1 o drive monitor output - channel 1: if no transmitted ami signal is present on mtip1 and mring1 input pins for 12832 txclk periods, then dmo1 will toggle and remain "high" until the next ami signal is detected. 5 dgnd **** transmit digital gnd (for transmitter 1) 6 agnd analog gnd (substrate connection) - channel 1 7 dvdd **** receive digital vdd (for receiver 1) ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 4 8 host/(hw )i host/hw mode select: this input pin permits the user to enable or disable the microprocessor serial interface (e.g., consisting of the sdi, sdo, sclk, and csb pins). setting this input pin "high" enables the microprocessor serial interface (or configures the XRT7302 to operate in the "host" mode). in this mode, the user is expected to configure the XRT7302 via the microprocessor serial inter- face. as a consequence, when the XRT7302 is operating in the "host" mode, then it will ignore the states of many of the discrete input pins. setting this input pin "low" disables the microprocessor serial interface (e.g., configures the XRT7302 to operate in the "hardware" mode). in this mode, many of the external input control pins will be functional and therefore the unsued input pins should not be left floating. 9 rxclk1 o receive clock output pin - channel 1: this output pin is the recovered clock signal from the incoming line signal, which is being received by channel 1. the receive section of channel 1 will output data via the rpos1 and rneg1 output pins, on the rising edge of this clock signal. n ote : the user can configure the receive section of channel 1 to update the data on the rpos1 and rneg1 output pins, on the falling edge of rxclk1, by doing one of the following: 1. if the XRT7302 is operating in the hardware mode pulling the "rclkinv" pin (pin 42) to "high". 2. if the XRT7302 is operating in the host mode writing a "1" into the "rclk(n)inv" bit-field within the command register. 10 rneg1 o receive negative pulse output - channel 1: this output pin will pulse "high" whenever channel 1, within the XRT7302 has received a "negative polarity" pulse, in the incoming line signal, at the rtip1/ rring1 inputs. n ote : note: if the b3zs/hdb3 decoder (within channel 1) is "enabled" then the "zero suppression" patterns, in the incoming line signal (such as: "00v", "000v", "b0v", "b00v") will not be reflected at this output. 11 rpos1 o receive positive pulse output - channel 1: this output pin will pulse "high" whenever channel 1, within the XRT7302 has received a "positive polarity" pulse, in the incoming line signal, at the rtip1/ rring1 inputs. n ote : if the b3zs/hdb3 decoder (within channel 1) is "enabled" then the "zero suppression" patterns, in the incoming line signal (such as: "00v", "000v", "b0v", "b00v") will not be reflected at this output. 12 dgnd **** receive digital gnd - channel 1 13 rlos1 o receive loss of signal output indicator - channel 1: this output pin toggles "high" if channel 1, within the XRT7302 has detected a "loss of signal" condition in the incoming line signal. the exact criteria that the XRT7302 uses to declare an "los condition" depends upon whether the device is operating in the e3 or ds3/sts-1 mode and the state of the losthr1 pin. pin description p in #s ignal n ame t ype d escription XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 5 14 lcv1 o line code violation indicator - channel 1: whenever the receive section of channel 1 detects a line code violation, then it will pulse this output pin "high". this output pin will remain "low" at all other times. the XRT7302 will output an nrz pulse via this output pin. hence, the user is advised to sample this output pin via the rxclk2 clock output signal. 15 rlol1 o receive loss of lock output indicator - channel 1: this output pin toggles "high" if channel 1, within the XRT7302 has detected a "loss of lock" condition. channel 1 will declare an lol (loss of lock) condi- tion if the recovered clock frequency deviates from the reference clock fre- quency (available at the exclk input pin) by more than 0.5%. 16 exclk1 i external reference clock input - channel 1: the user is expected to apply a 34.368 mhz clock signal (for e3 applications), a 44.736 mhz clock signal (for ds3 applications), or a 51.84 mhz clock signal (for sonet sts-1 applications). n otes : 1. it is permissible for one to use the same clock, which is also driving the "txclk" input pin. 2. it is permissible to operate channel 1 at a different data rate than from channel 2. 17 cs /(endecdis) i microprocessor serial interface - chip select input/encoder-decoder disable input: the exact functionality of this pin depends upon whether the XRT7302 is oper- ating in the host or hardware mode. host mode operation - chip select input (for the microprocessor serial interface): the local microprocessor must assert this pin (e.g., set it to "0") in order to enable communication with the XRT7302, via the microprocessor serial inter- face. (note: this pin is internally pulled "high".) hardware mode - b3zs/hdb3 encoder & decoder disable: setting this input pin "high" disables the "b3zs/hdb3 encoder & decoder" blocks (within the XRT7302) and configures the XRT7302 to transmit and receive the line signal in an ami format. conversely, setting this input pin "low" enables the "b3zs/hdb3 encoder & decoder" blocks and configures the XRT7302 to transmit and receive the line signal in the b3zs format, (for ds3/ sts-1 operation) or in the hdb3 format, (for e3 operation). n ote : if the XRT7302 is operating in the "hardware" mode, then this pin set- ting configures the "b3zs/hdb3" encoder and decoder blocks for both chan- nels 1 and 2. pin description p in #s ignal n ame t ype d escription ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 6 18 sclk/(rxoff2) i microprocessor serial interface clock signal/"channel 2 receiver shut off" input: the exact role that this particular pin plays depends upon whether the XRT7302 is operating in the "host" mode or in the "hardware" mode. host mode - microprocessor serial interface clock signal: this signal will be used to sample the data, on the sdi pin, on the rising edge. additionally, during "read" operations, the microprocessor serial interface will update the sdo output on the falling edge of this signal. hardware mode - channel 2 receiver shut off input pin: setting this input pin "high" shuts off the receive section within channel 2. conversely, setting this input pin "low" enables the receive section for full operation. 19 sdi/(rxoff1) i serial data input for the microprocessor serial interface/channel 1 - receiver shut off input pin: the exact function of this input depends upon whether the XRT7302 is operat- ing in the "host" mode or in the "hardware" mode. host mode - serial data input for the microprocessor serial interface: whenever the user wishes to read or write data into the command registers, over the microprocessor serial interface; the user is expected to apply the "read/write" bit, the address values (of the command registers) and data value to be written (during "write" operations) to this pin. this input will be sampled on the rising edge of the sclk pin (pin 18). hardware mode - channel 1 receiver shut off input pin: setting this input pin "high" shuts off the receive section within channel 1. conversely, setting this input pin "low" enables the receive section for full operation. 20 sdo/(e3_ch1) i/o serial data output from the microprocessor serial interface/e3_mode select - channel 1: the exact functionality of this pin depends upon whether the XRT7302 is oper- ating in the "host" mode or in the "hardware" mode. host mode operation - serial data output for the microprocessor serial interface: this pin will serially output the contents of the specified command register, during "read" operations. the data, on this pin, will be updated on the falling edge of the sclk input signal. this pin will be tri-stated upon completion of data transfer. hardware mode operation - e3 mode select - channel 1: this input pin permits the user to configure channel 1 (within the XRT7302) to operate in the e3 or sts/ds3 modes. setting this input pin to "high" config- ures channel 1 to operate in the "e3" mode. setting this input pin to "low" configures channel 1 to operate in either the ds3 or sts-1 modes (depend- ing upon the state of the "sts-1/ds3 _ch1 input pin (pin 21). pin description p in #s ignal n ame t ype d escription XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 7 21 sts-1/ds3 _ch1 i sts-1/ds3 select input - channel 1: a "high" on this pin configures the clock recovery phase locked loop (within channel 1) to set its vco center frequency to around 51.84 mhz (optimal for sonet sts-1 operations). a "low" on this pin configures the clock recovery phase locked loop to set the vco center frequency to 44.736 mhz (optimal for ds3 operations). n otes : 1. the XRT7302 will ignore this pin if the "e3_ch1" pin (pin 20) is set to "1". 2. this input pin is ignored if the XRT7302 is operating in the "host" mode. 3. the user should tie this pin to gnd, if the XRT7302 is going to be operating in the "host" mode. 22 ict i in-circuit test input setting this pin "low" causes all digital and analog outputs to go into a high- impedance state to allow for in-circuit testing. hence, the user should set this pin "high" for normal operation. n ote : this pin is internally pulled "high". 23 losthr1 i loss of signal threshold control - channel 1 the voltage forced on this pin controls the input loss of signal threshold for channel 1. forcing the losthr1 pin to gnd or vdd provides two settings. this pin must be set to the desired level upon power up and should not be changed during operation. n ote : this pin is only applicable during ds3 or sts-1 operations. 24 llb1 i local loop-back - channel 1 this input pin, along with "rlb1" dictates which loop-back mode channel 1 (within the XRT7302) will be operating in. a "high" on this pin (with "rlb1" being set to "low") configures channel 1, within the XRT7302 to operate in the "analog local loop-back" mode. a "high" on this pin (with "rlb1" also being set to "high") configures channel 1, within the XRT7302, to operate in the "digital local loop-back" mode and tristates the channel 1 transmitter output. n otes : 1. this input pin is ignored if the XRT7302 is operating in the "host" mode. 2. the user should tie this pin to gnd, if the XRT7302 is going to be operating in the "host" mode. pin description p in #s ignal n ame t ype d escription ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 8 25 rlb1 i remote loop-back - channel 1: this input pin, along with "llb1" dictates which loop-back mode "channel 1 (within the XRT7302) will be operating in. a "high" on this pin (with "llb1" being set to "low") configures channel 1, within the XRT7302 to operate in the remote loop-back mode. a "high" on this pin (with "llb1" also being set to "high") configures channel 1, within the XRT7302, to operate in the "digital local loop-back" mode and tristates the channel 1 transmitter output. n otes : 1. this input pin is ignored if the XRT7302 is operating in the "host" mode. 2. the user should tie this pin to gnd, if the XRT7302 is going to be operating in the "host" mode. 26 avdd **** receive analog vdd - channel 1: 27 rring1 i receive ring input - channel 1: this input pin, along with rtip1 is used to receive the bipolar line signal from the "remote ds3/e3 terminal". 28 rtip1 i receive tip input - channel 1: this input pin, along with rring1 is used to receive the bipolar line signal from the "remote ds3/e3/sts-1 terminal". 29 agnd **** receive analog gnd - channel 1 30 reqen1 i receive equalization enable input - channel 1: setting this input pin "low" disables the internal receive equalizer, within channel 1. setting this pin "high" enables the internal receive equalizer. the guidelines for enabling and disabling the receive equalizer are described in section 3.2 n otes : 1. this input pin is ignored if the XRT7302 is operating in the "host" mode. 2. the user should tie this pin to gnd, if the XRT7302 is going to be operating in the "host" mode. 31 reqen2 i receive equalization enable input - channel 2: setting this input pin "high" enables the internal receive equalizer, within channel 2. setting this pin "low" disables the internal receive equalizer. the guidelines for enabling and disabling the receive equalizer are described in section 3.2. n otes : 1. this input pin is ignored if the XRT7302 is operating in the "host" mode. 2. the user should tie this pin to gnd, if the XRT7302 is going to be operating in the "host" mode. 32 agnd **** receive analog gnd - channel 2 pin description p in #s ignal n ame t ype d escription XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 9 33 rtip2 i receive tip input - channel 2: this input pin, along with rring2 is used to receive the bipolar line signal from the "remote ds3/e3/sts-1 terminal". 34 rring2 i receive ring input - channel 2: this input pin, along with rtip2 is used to receive the bipolar line signal from the "remote ds3/e3 terminal". 35 avdd **** receive analog vdd - channel 2 36 rlb2 i remote loop-back - channel 2: this input pin, along with "llb2" dictates which loop-back mode "channel 2" (within the XRT7302) will be operating in. a "high" on this pin (with "llb2" being set to "low") configures channel 2, within the XRT7302 to operate in the "remote loop-back" mode. a "high" on this pin (with "llb1" also being set to "high") configures channel 2, within the XRT7302, to operate in the "analog local loop-back" mode and tristates the channel 2 transmitter output. n otes : 1. this input pin is ignored if the XRT7302 is operating in the "host" mode. 2. the user should tie this pin to gnd, if the XRT7302 is going to be operating in the "host" mode. 37 llb2 i local loop-back - channel 2: this input pin, along with "rlb2" dictates which loop-back mode channel 2 (within the XRT7302) will be operating in. a "high" on this pin (with "rlb2" being set to "low") configures channel 2 within the XRT7302 to operate in the "analog local loop-back" mode. a "high" on this pin (with "rlb2" also being set to "high") configures channel 2, within the XRT7302, to operate in the "digital local loop-back" mode and tristates the channel 2 transmitter output. n otes : 1. this input pin is ignored if the XRT7302 is operating in the "host" mode. 2. the user should tie this pin to gnd, if the XRT7302 is going to be operating in the "host" mode. 38 losthr2 i loss of signal threshold control - channel 2 the voltage forced on this pin controls the input loss of signal threshold for channel 2. two settings are provided by forcing the losthr2 pin to gnd or vdd. this pin must be set to the desired level upon power up and should not be changed during operation. n ote : this pin is only applicable during ds3 or sts-1 operations. pin description p in #s ignal n ame t ype d escription ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 10 39 e3_ch2 i e3 select input - channel 2: a "high" on this pin configures channel 2 of the XRT7302 to operate in the e3 mode. a "low" on this pin configures channel 2 of the XRT7302 to check the state of the sts-1/(ds3 _ch2) input pin n otes : 1. this input pin is ignored if the XRT7302 is operating in the "host" mode. 2. the user should tie this pin to gnd, if the XRT7302 is going to be operating in the "host" mode. 40 sr/dr i receive output single-rail/dual-rail select: setting this pin "high" configures the receive sections of both channels, to output data (in a single-rail manner) to the terminal equipment. setting this pin "low" configures the receive section of both channels, to output data (in a dual-rail manner) to the terminal equipment. 41 sts-1/ds3 _ch2 i sts-1/ds3 select input - channel 2: a "high" on this pin configures the clock recovery phase locked loop (in channel2 ) to set its vco center frequency to around 51.84 mhz (optimal for sonet sts-1 operations). a "low" on this pin configures the clock recovery phase locked loop to set its vco center frequency to around 44.736 mhz (optimal for ds3 operations). n otes : 1. the XRT7302 will ignore this pin if the e3_ch2 pin (pin 39) is set to "1". 2. this input pin is ignored if the XRT7302 is operating in the "host" mode. 3. the user should tie this pin to gnd, if the XRT7302 is going to be operating in the "host" mode. pin description p in #s ignal n ame t ype d escription XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 11 42 regr / (rclknv) i register reset input pin (invert rxclk(n) output - select): the exact function of this particular pin depends upon whether the XRT7302 is operating in the "host" mode or in the "hardware" mode. host-mode - register reset input pin: setting this input pin "low" causes the XRT7302 to reset the contents of the command registers to their default settings. additionally, it resets the XRT7302 to its "default" operating configuration. n ote : this pin is internally pulled "high". hardware mode - invert rxclk output select: setting this input pin "high" configures the receive section of both channels (within the XRT7302) to invert their "rxclk1 and rxclk2" clock output signals. specifically, setting this pin "low" configures channel 1 to output the recovered data (via the rpos1 and rneg1 output pins) on the "rising" edge of the rxclk1 output signal. this setting also configures channel 2 to output the recovered data (via the rpos2 and rneg2 output pins) on the "rising" edge of the rxclk2 output signal. conversely, setting this input pin "high" configures channel 1 to output the recovered data (via the rpos1 and rneg1 output pins) on the "falling" edge of the rxclk1 output signal. this setting also configures channel 2 to output the recovered data (via the rpos2 and rneg2 output pins on the "falling" edge of the rxclk2 output signal 43 gnd **** exclk reference gnd 44 vdd **** exclk reference vdd 45 exclk2 i external reference clock input: the user is expected to apply a 34.368 mhz clock signal (for e3 applications), a 44.736 mhz clock signal (for ds3 applications), or a 51.84 mhz clock signal (for sonet sts-1 applications). n otes : 1. it is permissible for one to use the same clock, which is also driving the "txclk" input pin. 2. it is permissible to operate channel 2 at a different data rate than from channel 1. 46 rlol2 o receive loss of lock output indicator - channel 2 this output pin toggles "high" if the receive section of channel 2 has detected a "loss of lock" condition. channel 2 will declare an lol (loss of lock) condition if the recovered clock frequency (at channel 2) deviates from the reference clock frequency (available at the exclk input pin) by more than 0.5%. 47 lcv2 o line code violation indicator - channel 2 whenever the receive section of channel 2 detects a line code violation, then it will pulse this output pin "high". this output pin will remain "low" at all other times. n ote : the XRT7302 will output an nrz pulse via this output pin. hence, the user is advised to sample this output pin via the rxclk2 clock output signal. pin description p in #s ignal n ame t ype d escription ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 12 48 rlos2 o receive loss of signal output indicator - channel 2 this output pin toggles "high" if receive section of channel 2 has detected a "loss of signal" condition in the incoming line signal. the exact criteria that the XRT7302 uses to declare an "los condition" depends upon whether the device is operating in the e3 or ds3/sts-1 mode. 49 dgnd **** receive digital ground - channel 2 50 rpos2 o receive positive pulse output - channel 2: this output pin will pulse "high" whenever the receive section of channel 2 has received a "positive polarity" pulse, in the incoming line signal, at the rtip/rring inputs. n ote : note: if the b3zs/hdb3 decoder (within channel 2) is "enabled" then the "zero suppression" patterns, in the incoming line signal (such as: "00v", "000v", "b0v", "b00v") will not be reflected at this output. 51 rneg2 o receive negative pulse output - channel 2: this output pin will pulse "high" whenever the receive section of channel 2 has received a "negative polarity" pulse, in the incoming line signal, at the rtip/rring inputs. n ote : note: if the b3zs/hdb3 decoder (within channel 2) is "enabled" then the "zero suppression" patterns, in the incoming line signal (such as: "00v", "000v", "b0v", "b00v") will not be reflected at this output. 52 rxclk2 o receive clock output pin - channel 2: this output pin is the recovered clock signal from the incoming line signal, which is being received via channel 2. the receive section of channel 2 will output data via the rpos2 and rneg2 output pins, on the rising edge of this clock signal. n ote : the user can configure the receive section of channel 2 to update the data on the rpos2 and rneg2 output pins, on the falling edge of rxclk2, by doing one of the following: 1. if the XRT7302 is operating in the hardware mode pulling the "rclkinv" pin (pin 42) to "high". 2. if the XRT7302 is operating in the host mode writing a "1" into the "rclk(n)inv" bit-field within the command register. pin description p in #s ignal n ame t ype d escription XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 13 53 losmuten i mute-upon-los enable input (hardware mode): this input pin permits the user to configure the XRT7302 (while it is operating in the "hardware mode") to mute the recovered data (via the rpos1, rneg1, rpos2 and rneg2 output pins), whenever the corresponding channel declares an los conditions. setting this input pin "high" will configure channel 1 to automatically pull the rpos1 and rneg1 output pins to "gnd", whenever it is declaring an los condition (thereby muting the data being output to the terminal equipment). similarly, channel 2 will automatically pull the rpos 2 and rneg2 output pins to "gnd" whenever it is declaring an los condition. setting this input pin "low" configures channels 1 and 2 to not automatically mute the recovered data, whenever an los condition is declared. n otes : 1. this pin will be ignored if the XRT7302 is operating in the "host" mode. 2. the user should tie this pin to gnd, if the XRT7302 is to be operated in the "host" mode. 3. this pin is internally pulled "high". 54 dvdd **** receive digital vdd - channel 2 55 agnd **** analog ground (substrate connection) - channel 2 56 dgnd **** transmit digital gnd - channel 2 57 dmo2 o drive monitor output - channel 2: if no transmitted ami signal is present on the mtip2 and mring2 input pins for 12832 txclk periods, then dmo2 will toggle and remain "high" until the next ami signal is detected. 58 dvdd **** transmit digital vdd - channel 2 59 ta o s 2 i transmit all ones select - channel 2: a "high" on this pin causes the transmit section, within channel 2 to generate and transmit a continuous ami "all 1s" pattern to be transmitted onto the line. the frequency of this "1s" pattern is determined by txclk2. n otes : 1. this input pin is ignored if the XRT7302 is operating in the "host" mode. 2. the user should tie this pin to gnd, if the XRT7302 is going to be operating in the "host" mode. pin description p in #s ignal n ame t ype d escription ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 14 60 txlev2 i transmit line build-out enable/disable select - channel 2: this input pin permits the user to enable or disable the transmit line build-out circuit, within channel 2 of the XRT7302. setting this pin to "high" disables the line build-out circuit within channel 2. in this mode, channel 2 will output unshaped (e.g., square-wave) pulses onto the line via the ttip2 and tring2 output pins. setting this pin to "low" enables the line build-out circuit within channel 2. in this mode, channel 2 will output shaped pulses onto the line via the ttip2 and tring2 output pins. in order to comply with the "isolated dsx-3/stsx-1 pulse template require- ments (per bellcore gr-499-core or bellcore gr-253-core), the user should: a. set this input pin to "1", if the cable length (between the cross-connect and the transmit output of channel 2) is greater than 225 feet. b. set this input pin to "0", if the cable length (between the cross-connect and the transmit output of channel 2) is less than 225 feet. this pin is active only if the following two conditions are true: a. the XRT7302 is configured to operate in either the ds3 or sonet sts-1 modes. b. the XRT7302 is configured to operate in the "hardware" mode. n ote : the user should tie this pin to gnd if the XRT7302 is going to be oper- ating in the "host" mode. 61 txoff2 i transmitter off input - channel 2: setting this input pin "high" configures the XRT7302 to turn off the transmit section within channel 2. in this mode, the ttip2 and tring2 outputs will be tri-stated. n otes : 1. this input pin controls the ttip2 and tring2 outputs, even when the XRT7302 is operating in the "host" mode. 2. for host mode operation, the user should tie this pin to gnd, to turn- on/turn-off the transmitter via the microprocessor serial interface. 62 txclk2 i transmit clock input for tpdata2 and tndata2 - channel 2: this input pin must be driven at 34.368 mhz (for e3 applications), 44.736 mhz (for ds3 applications), or 51.84 mhz (for sonet sts-1 applications). the transmit section of channel 2 will use this signal to sample the tpdata2 and tndata2 input pins. by default, channel 2 will be configured to sample these two pins on the falling edge of this signal. if the XRT7302 is operating in the "host" mode, then channel 2 can be config- ured to sample the tpdata2 and tndata2 input pins on either the rising or falling edge of txclk2. pin description p in #s ignal n ame t ype d escription XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 15 63 tpdata2 i transmit positive data input - channel 2: the transmit section of channel 2 will sample this pin, on the falling edge of txclk2. if the channel samples a "1" at this input pin, then it will generate and transmit a "positive" polarity pulse to the line. n otes : 1. the data should be applied to this input pin if the "transmit section" is configured to accept single-rail data from the terminal equipment. 2. if the XRT7302 is operating in the "host" mode, then the user can (if desired) configure channel 2 to sample the tpdata2 pin on either the rising or falling edge of txclk2. 64 tndata2 i transmit negative data input - channel 2: the transmit section of channel 2 will sample this pin, on the falling edge of txclk2. if the device samples a "1" at this input pin, then it will generate and transmit a "negative" polarity pulse to the line. n otes : 1. this input pin will be ignored and should be tied to gnd, if the trans- mit section is configured to accept "single-rail" data from the termi- nal equipment. 2. if the XRT7302 is operating in the "host" mode, then the user can (if desired) configure channel 2 to sample the tndata2 pin on either the rising or falling edge of txclk2. 65 mtip2 i monitor tip input - channel 2: the bipolar line output signal, from ttip2 can be connected to this pin, via a 270-ohm resistor, in order to check for line driver failure. this pin is internally pulled "high". 66 mring2 i monitor ring input - channel 2: the bipolar line output signal, from tring2 can be connected to this pin, via a 270-ohm resistor, in order to check for line driver failure. this pin is internally pulled "high". 67 avdd **** transmit analog vdd - channel 2: 68 ttip2 o transmit ttip output - channel 2: the XRT7302 will use this pin, along with tring2, to transmit a bipolar line signal, via a 1:1 transformer. 69 tring2 o transmit ring output - channel 2: the XRT7302 will use this pin, along with ttip2, to transmit a bipolar line sig- nal, via a 1:1 transformer. 70 agnd **** transmit analog gnd - channel 2 71 agnd **** transmit analog gnd - channel 1 72 tring1 o transmit ring output - channel 1: the XRT7302 will use this pin, along with ttip1, to transmit a bipolar line sig- nal, via a 1:1 transformer. pin description p in #s ignal n ame t ype d escription ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 16 73 ttip1 o transmit ttip output - channel 1: the XRT7302 will use this pin, along with tring1, to transmit a bipolar line signal, via a 1:1 transformer. 74 avdd **** transmit analog vdd - channel 1 75 mring1 i monitor ring input - channel 1: the bipolar line output signal, from tring1 can be connected to this pin, via a 270-ohm resistor, in order to check for line driver failure. this pin is internally pulled "high". 76 mtip1 i monitor tip input - channel 1: the bipolar line output signal, from ttip1 can be connected to this pin, via a 270-ohm resistor, in order to check for line driver failure. this pin is internally pulled "high". 77 tndata1 i transmit negative data input - channel 1: the XRT7302 will sample this pin, on the falling edge of txclk1. if the device samples a "1" at this input pin, then it will generate and transmit a "negative" polarity pulse to the line. n otes : 1. this input pin will be ignored and should be tied to gnd, if the trans- mit section is configured to accept "single-rail" data from the termi- nal equipment. 2. if the XRT7302 is operating in the "host" mode, then the user can (if desired) configure the XRT7302 to sample the tndata pin on either the rising or falling edge of txclk. 78 tpdata1 i transmit positive data input - channel 1 the XRT7302 will sample this pin, on the falling edge of txclk. if the device samples a "1" at this input pin, then it will generate and transmit a "positive" polarity pulse to the line. n otes : 1. the data should be applied to this input pin if the "transmit section" is configured to accept single-rail data from the terminal equipment. 2. if the XRT7302 is operating in the "host" mode, then the user can (if desired) configure the XRT7302 to sample the tpdata pin on either the rising or falling edge of txclk. 79 txclk1 i transmit clock input for tpdata and tndata - channel 1: this input pin must be driven at 34.368 mhz (for e3 applications), 44.736 mhz (for ds3 applications), or 51.84 mhz (for sonet sts-1 applications). the XRT7302 will use this signal to sample the tpdata and tndata input pins. by default, the XRT7302 will be configured to sample these two pins on the falling edge of this signal. if the XRT7302 is operating in the "host" mode, then the device can be config- ured to sample the tpdata and tndata input pins on either the rising or falling edge of txclk. pin description p in #s ignal n ame t ype d escription XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 17 80 txoff1 i transmitter off input - channel 1: setting this input pin "high" configures the XRT7302 to turn off the transmit section within channel 1. in this mode, the ttip1 and tring1 outputs will be tri-stated. n otes : 1. this input pin controls the ttip1 and tring2 outputs, even when the XRT7302 is operating in the "host" mode. 2. for host mode operation, the user should tie this pin to gnd, to turn- on/turn-off the transmitter via the microprocessor serial interface. pin description p in #s ignal n ame t ype d escription ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 18 electrical characteristics n ote : the XRT7302 is assembled in a thermally enhanced package with an intergral copper heat slug. the heat slug is solder plated on the bottom of the package and is electri- cally connected to the ground connections of the device. this heat slug can be soldered to the mounting board if desired, but must be isolated from any v dd connections. n ote : * not applicable to pins with pull-down resistors. absolute maximum ratings storage temperature - 65 0 c to + 150 0 c operating temperature - 40 0 c to + 85 0 c supply voltage range -0.5v to +6.0v theta-ja 23 c/w theta-jc 5.32 c/w e lectrical c haracteristics (t a = 25 0 c, v dd = 5v + 5%, unless otherwise specified ) s ymbol p arameter m in . typ .m ax .u nits dc electrical characteristics v ddd dc supply voltage (digital) 4.75 5 5.25 v v dda dc supply voltage (analog) 4.75 5 5.25 v i cc supply current (measured while transmitting and receiving all "1s" ds3 mode sts-1 mode 335 360 400 440 ma ma v il input low voltage 0.8 v v ih input high voltage 2.0 v dd v v ol output low voltage, iout = -4.0ma 0 0.4 v v oh output high voltage, iout = 4.0ma 2.8 v dd v i l input leakage current* 10 a XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 19 e lectrical c haracteristics (c ontinued ) (t a = 25 0 c, v dd = 5v + 5%, unless otherwise specified ) ac e lectrical c haracteristics (s ee ? igure 1) t erminal s ide t iming p arameters ( see ? igure 2 and ? igure 3) s ymbol p arameter m in . typ .m ax .u nits txclk1, txclk2 clock duty cycle (ds3/sts-1) 30 50 70 % txclk1, txclk2 clock duty cycle (e3) 30 50 70 % txclk1, txclk2 frequency (sonet sts-1) 51.84 mhz txclk1, txclk2 frequency (ds3) 44.736 mhz txclk1, txclk2 frequency (e3) 34.368 mhz t rtx txclk1, txclk2 clock rise time (10% to 90%) 4.0 ns t ftx txclk1, txclk2 clock fall time (90% to 10%) 4.0 ns t tsu tpdata/tndata to txclk1, 2 falling set up time 3.0 ns t tho tpdata/tndata to txclk1, 2 falling hold time 3.0 ns t lcvo rxclk1, 2 to rising edge of lcv1, 2 output delay 2.5 ns t tdy ttip1, 2/tring1, 2 to txclk1, 2 rising propagation delay time 0.6 14.0 ns rxclk1, rxclk2 clock duty cycle 45 50 55 % rxclk1, rxclk2 frequency (sonet sts-1) 51.84 mhz rxclk1, rxclk2 frequency (ds3) 44.736 mhz rxclk1, rxclk2 frequency (e3) 34.368 mhz t co rxclk1, 2 to rpos1, 2/rneg1, 2 delay time 4.0 ns t rrx rxclk1, rxclk2 clock rise time (10% to 90%) 2.0 4.0 ns t frx rxclk1, rxclk2 clock fall time (10% to 90%) 1.5 3.0 ns c i input capacitance 10 pf c l load capacitance 10 pf ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 20 f igure 1. t ransmit p ulse a mplitude t est c ircuit for e3, ds3 and sts-1 r ates ( typical channel shown ) f igure 2. t iming d iagram of the t ransmit t erminal i nput i nterface txpos(n) txneg(n) txlineclk(n) ttip(n) tring(n) tpos(n) tneg(n) txclk(n) channel (n) t1 r1 36 w r2 36 w 1:1 75 w r3 tpdata or tndata ttip or tring tclk t tsu t tho t rtx t ftx t tdy f igure 3. t iming d iagram of the r eceive t erminal o utput i nterface rclk t rrx t frx rpos or rneg lcv t lcvo t co XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 21 e lectrical c haracteristics (c ontinued ), (t a = 25 0 c, v dd = 5v + 5%, unless otherwise specified ) l ine s ide p arameters e3 a pplication s ymbol p arameter m in .t yp .m ax u nits t ransmit c haracteristics ( see ? igure 2) transmit output pulse amplitude (measured at secondary output of transformer, see figure 1) 0.9 1.0 1.1 vpk transmit output pulse amplitude ratio 0.95 1.00 1.05 transmit output pulse width 12.5 14.55 16.5 ns transmit output pulse width ratio 0.95 1.00 1.05 transmit output jitter with jitter-free input @ txclk(n) 0.02 0.05 uipp receive line characteristics (see ?igure 3) receive sensitivity (length of cable) 1100 feet interference margin -20 -17 db signal level to declare loss of signal -35 db signal level to clear loss of signal -15 db occurrence of los to los declaration time 10 100 255 ui termination of los to los clearance time 10 100 255 ui intrinsic jitter (all ones pattern) (1) 0.01 ui intrinsic jitter (all 100 pattern) 0.03 ui jitter tolerance @ jitter frequency = 100hz 64 ui jitter tolerance @ jitter frequency = 1khz 30 ui jitter tolerance @ jitter frequency = 10khz 4 ui jitter tolerance @ jitter frequency = 800khz 0.15 ui e lectrical c haracteristics (c ontinued ), (t a = 25 0 c, v dd = 5v + 5%, unless otherwise specified ) l ine s ide p arameters s onet sts-1 a pplication t ransmit c haracteristics (s ee f igure 2) s ymbol p arameter m in .t yp .m ax u nits transmit output pulse amplitude (measured with txlev=0, see figure 1) 0.68 0.75 0.85 vpk transmit output pulse amplitude (measured with txlev=1, see figure 1) 0.93 0.98 1.08 vpk transmit output pulse width 8.6 9.65 10.6 ns transmit output pulse amplitude ratio 0.9 1.0 1.1 transmit output jitter with jitter-free input @ txclk(n) 0.02 0.05 ui receive line characteristics (see figure 3) ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 22 (1) measured with equalizer enabled, 12db cable attenuation, v dd = 5v and t a = 25c (2) measured at nominal stsx-1 level with equalizer enabled, v dd = 5v and t a = 25c receive sensitivity (length of table) 900 feet signal level to declare loss of signal (losthr = 0, req_in = 1) 75 mv signal level to clear loss of signal (losthr = 0, req_in = 1) 270 mv signal level to declare loss of signal (losthr = 1, req_in = 1) 25 mv signal level to clear loss of signal (losthr = 1, req_in = 1) 110 mv signal level to declare loss of signal (losthr = 0, req_in = 0) 55 mv signal level to clear loss of signal (losthr = 0, req_in = 0) 210 mv signal level to declare loss of signal (losthr = 1, req_in = 0) 90 mv signal level to clear loss of signal (losthr = 1, req_in = 0) 90 mv intrinsic jitter (all ones pattern) (2) 0.03 ui intrinsic jitter (all ones pattern) 0.03 ui jitter tolerance @ jitter frequency = 100hz 64 ui jitter tolerance @ jitter frequency = 1khz 64 ui jitter tolerance @ jitter frequency = 10khz 5 ui jitter tolerance @ jitter frequency = 800khz 0.4 ui e lectrical c haracteristics (c ontinued ), (t a = 25 0 c, v dd = 5v + 5%, unless otherwise specified ) l ine s ide p arameters s onet sts-1 a pplication t ransmit c haracteristics (s ee f igure 2) s ymbol p arameter m in .t yp .m ax u nits e lectrical c haracteristics (c ontinued ), (t a = 25 0 c, v dd = 5v + 5%, unless otherwise specified ) l ine s ide p arameters ds3 a pplication s ymbol p arameter m in .t yp .m ax u nits t ransmit c haracteristics ( see ? igure 2) transmit output pulse amplitude (measured a 0 feet, txlev=0, see figure 1) 0.68 0.75 0.85 vpk transmit output pulse amplitude (measured a 0 feet, txlev=1, see figure 1) 0.9 1.0 1.1 vpk transmit output pulse width 10.10 11.18 12.28 ns transmit output pulse amplitude ratio 0.9 1.0 1.1 transmit output jitter with jitter-free input @ txclk(n) 0.02 0.05 ui receive line characteristics (see ?igure 3) XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 23 (1) measured at nominal dsx3 level, equalizer en- abled, v dd = 5v, t a = 25c receive sensitivity (length of cable) 900 feet receive intrinsic jitter (all ones pattern) 0.01 ui receive intrinsic jitter (using prbs 2 23-1 pattern) 0.02 ui signal level to declare loss of signal (losthr = 0, req_in = 1) 55 mv signal level to clear loss of signal (losthr = 0, req_in = 1) 220 mv signal level to declare loss of signal (losthr = 1, req_in = 1) 22 mv signal level to clear loss of signal (losthr = 1, req_in = 1) 90 mv signal level to declare loss of signal (losthr = 0, req_in = 0) 35 mv signal level to clear loss of signal (losthr = 0, req_in = 0) 155 mv signal level to declare loss of signal (losthr = 1, req_in = 0) 17 mv signal level to clear loss of signal (losthr = 1, req_in = 0) 70 mv intrinsic jitter (all ones pattern) 0.01 ui intrinsic jitter (all 100 pattern) (1) ui jitter tolerance @ jitter frequency = 1khz 64 ui jitter tolerance @ jitter frequency = 10khz 5 ui jitter tolerance @ jitter frequency = 800khz 0.4 ui e lectrical c haracteristics (c ontinued ), (t a = 25 0 c, v dd = 5v + 5%, unless otherwise specified ) l ine s ide p arameters ds3 a pplication s ymbol p arameter m in .t yp .m ax u nits ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 24 n otes : 1. a4 and a5 are always "0". 2. r/w = "1" for "read" operations 3. r/w = "0" for "write" operations 4. a shaded pulse, denotes a dont care value. e lectrical c haracteristics (c ontinued ), (t a = 25 0 c, v dd = 5 + 5%, unless otherwise specified ) m icroprocessor s erial i nterface t iming (s ee ? igure 5) s ymbol p arameter m in .t yp .m ax u nits t 21 cs low to rising edge of sclk setup time 50 ns t 22 cs high to rising edge of sclk hold time 20 ns t 23 sdi to rising edge of sclk setup time 50 ns t 24 sdi to rising edge of sclk hold time 50 ns t 25 sclk "low" time 240 ns t 26 sclk "high" time 240 ns t 27 sclk period 500 ns t 28 cs low to rising edge of sclk hold time 50 ns t 29 cs "inactive" time 250 ns t 30 falling edge of sclk to sdo valid time 200 ns t 31 falling edge of sclk to sdo invalid time 100 ns t 32 falling edge of sclk, or rising edge of cs to high z 100 ns t 33 rise/fall time of sdo output 40 ns f igure 4. m icroprocessor s erial i nterface d ata s tructure d0 d1 d2 0 0 0 d4 d3 high z sdo a0 d0 r/w d1 a6 0 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 sdi 12345678910111213141516 sclk cs high z XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 25 f igure 5. t iming d iagram for the m icroprocessor s erial i nterface sdi r/w a1 a0 cs sclk cs sclk sdi sdo d0 d1 d2 d7 t22 t21 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 hi-z hi-z ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 26 system description a functional block diagram of the XRT7302 e3/ds3/ sts-1 transceiver ic is presented in figure 6. in general, the XRT7302 contains three distinct sec- tions: ? the transmit section - channels 1 and 2 ? the receive section - channels 1 and 2 ? the microprocessor serial interface each of these sections are briefly discussed below. the transmit section (channels 1 and 2) the transmit section, within each channel, accepts ttl/cmos level signals from the "terminal equip- ment" in either a "single-rail" or "dual rail" format. the transmit section will then take this data and do the following. ? encode this data into the b3zs format (if the ds3 or sonet sts-1 modes have been selected) or into the hdb3 format (if the e3 mode has been selected). ? convert the cmos level b3zs or hdb3 encoded data into pulses with shapes that are compliant with the various industry standard pulse template requirements. ? drive these pulses onto the line via the ttip and tring output pins, across a 1:1 transformer. n ote : note: the transmit section will drive a "1" (or a "mark") onto the line by driving either a positive or negative polarity pulse across the 1:1 transformer, within a given bit period. the transmit section will drive a "0" (or a "space") onto the line by driving no pulse onto the line. the receive section (channels 1 and 2) the receive section, within each channel, receives a bipolar signal from the line, through the rtip and rring pins via a "1:1 transformer" or via a "0.01f capacitor". the receive section will do the following. ? adjust the signal level through an agc circuit. ? optionally equalize this signal for cable loss. ? the "sliced" data will be routed to the "hdb3/b3zs" decoder; during which the data content (as trans- mitted by the remote terminal equipment) is restored to its original content. ? the recovered clock and data will be output to the "local terminal equipment", in the form of cmos level signals, via the rpos, rneg, rxclk1 and rxclk2 output pins. the microprocessor serial interface the XRT7302 can be configured to operate in either the "hardware" mode or the "host" mode. each of these modes will be discussed below. the hardware mode when the XRT7302 is operating in the "hardware mode", then the following is true. 1. the microprocessor serial interface block is disabled. 2. the XRT7302 is configured via input pin set- tings. the XRT7302 can be configured to operate in the "hardware mode" by tying the "host/hw " input pin (pin 8) to gnd. each of the pins associated with the microprocessor serial interface will take on their alternative role, as defined in table 1. additionally, when the XRT7302 is operating in the "hardware" mode, all of the remaining input pins be- come active. the host mode the XRT7302 can be configured to operate in the "host" mode by tying the "host/hw " input pin (pin 8) to vdd. when the XRT7302 is operating in the "host mode", then the following is true. 1. the microprocessor serial interface block is enabled. writing the appropriate data into the on-chip command registers makes many config- uration selections. 2. all of the following input pins are disabled. ? pin 1 - txlev1 ? pin 2 - taos1 ? pin 21 - sts-1/ds3 _ch1 ? pin 24 - llb1 t able 1: r ole of m icroprocessor s erial i nterface pins when the XRT7302 is operating in the "h ardware " m ode p in #p in n ame f unction , while in hardware mode 17 cs /(endecdis) endecdis 18 sclk/(rxoff2) rxoff2 19 sdi/(rxoff1) rxoff1 20 sdo/(e3_ch1) e3_ch1 42 regr/ (rclkinv) rcklkinv XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 27 ? pin 25 - rlb1 ? pin 30 - reqen1 ? pin 31 - reqen2 ? pin 36 - rlb2 ? pin 37 - llb2 ? pin 39 - e3_ch2 ? pin 41 - sts-1/ds3 _ch2 ? pin 59 - taos2 ? pin 60 - txlev2 the user is advised to tie each of these pins to gnd to operate the XRT7302 ic in the "host" mode. in host mode operation, the txoff1 and txoff2 input pins can still be used to turn on or turn off the transmit output drivers within channels 1 and 2, respectively. the intent behind this feature is to per- mit a system (designed for redundancy) to quickly switch out a defective line card, and switch-in the back-up line card. the remainder of this document presents a detailed description of the features associated with the XRT7302. 1.0 selecting the data rate each channel within the XRT7302 can be configured to support the e3 (34.368 mbps), ds3 (44.736 mbps) or the sonet sts-1 (51.84 mbps) rates. further, each channel can be configured to operate in a mode/data rate that is independent of the other chan- nel. the XRT7302 permits the user to select the data rate (for each channel) via one of two ways. 1.1 c onfiguring c hannel 1 a. when operating in the "hardware" mode. in order to configure channel 1 into the appropriate mode, the user must set the "e3_ch1", and the "sts-1/ds3 _ch1 input pins to the appropriate logic states, as presented below in table 2. f igure 6. f unctional b lock d iagram of the XRT7302 agc/ equalizer serial processor interface peak detector los detector pulse shaping hdb3/ b3zs encoder transmit logic duty cycle adjust slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder sdi sdo sclk cs regr ttip(n) tring(n) rtip(n) rring(n) reqen(n) rxclk(n) rpos(n) rneg(n) lcv(n) rlos(n) llb(n) rlb(n) taos(n) tpdata(n) tndata(n) txclk(n) e3_ch(n) sts-1/ds3_ch(n) host/hw rlol(n) exclk(n) rxclkinv channel 1 channel 2 device monitor tx control txlev(n) txoff(n) dmo(n) mtip(n) mring(n) endecdis notes: 1. (n) = 1 or 2 for the respective channel. 2. serial processor interface pins are shared by both channels in host mode and are redefined in hardware mode. losthr(n) rxoff(n) ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 28 b. when operating in the "host" mode. in order to configure channel 1 into the appropriate mode, the user must write the appropriate values into the "sts-1/ds3 _ch1" and "e3_ch1" bit-fields, within command register cr4, as illustrated below. table 3 relates the values of these two bit-fields to the selected data rates. by making these selections, the user is doing the following: ? configuring the vco center frequency of the clock recovery phase-locked-loop (within chan- nel 1) to match the selected data rate. ? configuring the "b3zs/(hdb3)" encoder and decoder blocks to support b3zs encoding/decod- ing, if the ds3 or sts-1 data rates were selected; or ? configuring the "b3zs/(hdb3)" encoder and decoder blocks to support hdb3 encoding/decod- ing, if the e3 data rate was selected. ? configuring the on-chip "pulse-shaping" circuitry to generate transmit output pulses, of the appropriate shape and width to meet the applicable pulse tem- plate requirement. ? establishes the los declaration/clearance criteria (for channel 1). (see section 3.6) 1.2 c onfiguring c hannel 2 a. when operating in the "hardware" mode in order to configure channel 2 into the appropriate mode, the user must set the e3_ch2 and the sts-1/(ds3 _ch2) input pins to the appropriate logic states as presented below in table 4. b. when operating in the "host" mode. in order to configure channel 2 into the appropriate mode, the user must write the appropriate values into t able 2: s electing the d ata r ate for c hannel 1, ( within the XRT7302), via the "e3_c h 1" and "sts-1/ ds3 _c h 1" input pins (h ardware m ode ) d ata r ate s tate of e3_ch1 p in (p in 20) s tate of sts-1/(ds3 _ch1) p in (p in 21) m ode of b3zs/hdb3 e ncoder / d ecoder b locks e3 (34.368 mbps) 1 x (don't care) hdb3 ds3 (44.736 mbps) 00 b3zs sts-1 (51.84 mbps) 01 b3zs command register, cr4 (address = 0x04) d4 d3 d2 d1 d0 x sts-1/(ds3 _ch1) e3_ch1 llb1 rlb1 x x xxx t able 3: s electing the d ata r ate for c hannel 1 ( within the XRT7302); via the "sts-1/ds3 _c h 1" and the "e3_c h 1" bit - fields , within c ommand r egister cr4 (h ost m ode ) s elected d ata r ate sts-1/(ds3 _c h 1) (d3) "e3_c h 1" (d2) e3 x (don't care) 1 ds3 0 0 sts-1 1 0 t able 4: s electing the d ata r ate for c hannel 2 ( within the XRT7302) via the "e3_c h 2" and "sts-1/ ds3 _c h 2" input pins (h ardware m ode ) d ata r ate s tate of e3_c h 2 p in (p in 39) s tate of sts-1/ ( ds3 _c h 2) p in (p in 41 m ode of b3zs/(hdb3) e ncoder /d ecoder b locks e3 (34.368 mbps) 1 x (don't care) hdb3 ds3 (44.736 mbps) 00 b3zs sts-1 (51.84 mbps) 01 b3zs XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 29 the "sts-1/(ds3 _ch2)" and "e3_ch2" bit-fields, with- in command register cr12, as illustrated below. table 5 relates the values of these two bit-fields to the selected data rates. by making these selections, the user is doing the following: ? configuring the vco center frequency of the clock recovery phase-locked-loop (within chan- nel 2) to match the selected data rate. ? configuring the "b3zs/(hdb3)" encoder and decoder blocks to support b3zs encoding/decod- ing, if the ds3 or sts-1 data rates were selected; or ? configuring the "b3zs/(hdb3)" encoder and decoder blocks to support hdb3 encoding/decod- ing, if the e3 data rate was selected. ? configuring the on-chip "pulse-shaping" circuitry to generate transmit output pulses, of the appropriate shape and width to meet the applicable pulse tem- plate requirement. ? establishes the los declaration/clearance criteria (for channel 2). (see section 3.6) n ote : the user is required to apply the appropriate clock signals to both the exclk1 and exclk2 input pins, in order for the "receive sections" (of channels 1 and 2) to function properly. 2.0 the transmit section figure 6 indicates that the transmit section, within each channel of the XRT7302 consists of the follow- ing blocks: ? transmit logic block ? the txclk duty cycle adjust block ? hdb3/(b3zs) encoder ? pulse shaping block each of these blocks will be discussed in some detail below in general, the purpose of the "transmit section", within each channel of the XRT7302, is to take ttl/ cmos level data, from the terminal equipment, and encode it into a format such that it can: 1. be efficiently transmitted over coaxial cable; at e3, ds3, or sts-1 data rates; and 2. be reliably received by the remote terminal equipment at the other end of the e3, ds3, or sts-1 data link. 3. comply with the applicable pulse template requirements. the circuitry that the transmit section, (within each channel of the XRT7302) takes to accomplish this goal is discussed below. n ote : the following discussion applies equally to both channels 1 and 2. hence, the transmit section signals will be referred to via their generic rates (e.g., txclk) as opposed to "txclk1" and "txclk2". 2.1 t he t ransmit l ogic b lock the purpose of the transmit logic block is to accept either dual-rail or single rail (e.g., a binary data stream) ttl/cmos level data and timing information from the terminal equipment. 2.1.1 accepting "dual-rail" data from the ter- minal equipment command register, cr12 (address = 0x0c) d4 d3 d2 d1 d0 x sts-1(/ ds3 _ch2) e3_ch2 llb2 rlb2 x x xxx t able 5: s electing the d ata r ate for c hannel 2 ( within the XRT7302) via the "e3_c h 2" and "sts-1/ ds3 _c h 2" b it f ields , within c ommand r egister cr4 (h ost m ode ) d ata r ate s tate of e3_c h 2 p in (p in 39) s tate of sts-1/ ( ds3 _c h 2) p in (p in 41 m ode of b3zs/(hdb3) e ncoder /d ecoder b locks e3 (34.368 mbps) 1 x (don't care) hdb3 ds3 (44.736 mbps) 00 b3zs sts-1 (51.84 mbps) 01 b3zs ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 30 whenever the XRT7302 accepts dual-rail data from the terminal equipment, it does so via the following input signals. ?tpdata ? tndata ?txclk figure 7 presents an illustration of the typical inter- face for the transmission of data in a "dual-rail" for- mat between the terminal equipment and the trans- mit section of the XRT7302. the manner that the liu handles "dual-rail" data is described below and is illustrated in figure 8. the transmit section (of a channel) will typically sample the data on the tpdata and tndata input pins on the falling edge of txclk. txclk is typically a clock signal that is of the selected data rate frequency. for the e3 data rate, txclk is 34.368 mhz. for the ds3 data rate, txclk is 44.736 mhz, and for the sonet sts-1 rate, txclk is 51.84 mhz. if the transmit section samples a "1" on the tpdata input pin, then the "transmit section" of the device will ultimately generate a positive polarity pulse via the ttip and tring output pins (across a 1:1 transformer). conversely, if the transmit section samples a "1" on the tndata input pin, then the "transmit section" of the device will ultimately gener- ate a negative polarity pulse via the ttip and tring output pins (across a 1:1 transformer). 2.1.2 accepting "single-rail" data from the terminal equipment f igure 7. i llustration of the typical interface for the t ransmission of d ata in a d ual r ail f or - mat , from the "t ransmitting " t erminal e quipment to the "t ransmit s ection " of a channel within the XRT7302 transmit logic block XRT7302 e3/ds3/sts-1 liu terminal equipment (e3/ds3 or sts-1 framer) tpdata tndata txclk txpos txneg txlineclk f igure 8. i llustration on how the XRT7302 s amples the data on the tpd ata and tnd ata input pins txclk tpdata tndata data 1 1 0 XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 31 if the user wishes to transmit data from the "terminal equipment" to the transmit section within a given channel in a "single-rail" format (e.g., a binary data stream), without having to convert it into a "dual-rail" format; the user can do the following. a. configure the XRT7302 to operate in the "host" mode. b. access the microprocessor serial interface, and execute the following steps, for each channel. to configure channel 1 to accept single-rail data from the terminal equipment: write a "1" into the "txbin1" (transmit binary) bit- field, within command register 1 (for channel 1), as depicted below. n ote : executing this write operating to command register 1 will not configure the transmit section (within channel 2) to accept "single-rail" data from the terminal equipment. to configure channel 2 to accept single-rail data from the terminal equipment: write a "1" into the "txbin2" bit-field, within com- mand register 9 (for channel 2), as depicted below. n ote : executing this write operating to command register cr9 will not configure the transmit section (within channel 2) to accept single-rail data from the terminal equipment. the transmit section (of each channel) will sample this input pin on the "falling" edge of the txclk clock signal, and will encode this data into the appropriate bipolar line signal across the ttip and tring output pins. n otes : 1. in this mode, the transmit logic block will ignore the tndata input pin. 2. if the user configures the transmit section (within a given channel) to accept "single-rail" data from the terminal equipment, then the user must enable the "b3zs/hdb3" encoder. figure 9 illustrates the behavior of the tpdata and txclk signals, when the transmit logic block has been configured to accept "single-rail" data from the terminal equipment 2.2 t he t ransmit c lock d uty c ycle a djust c ir - cuitry the on-chip "pulse-shaping" circuitry (within the transmit section of each channel in the XRT7302) generates pulses of the appropriate shapes and width, in order to meet the applicable pulse template requirement. the widths of these "output" pulses are defined by the width of the "half-period" pulses within the txclk signal. however, if the widths of the pulses, within the txclk clock signal are allowed to vary significantly, this could jeopardize the chip's ability to generate trans- mit output pulses of the appropriate width, and there- by failing the applicable "pulse template" requirement specification. as consequence, the chip's ability to generate compliant pulses could depend upon the duty cycle of the clock signal, applied to the txclk in- put pin. the transmit clock duty cycle adjust circuitry ac- cepts clock pulses from the txclk input pin with duty cycles ranging from 30% to 70%, and to regenerate these signals at a 50% duty cycle. command register 1 (address = 0x01) d4 d3 d2 d1 d0 txoff1 taos1 txclkinv1 txlev1 txbin1 xx x x 1 command register 9 (address = 0x09) d4 d3 d2 d1 d0 txoff2 taos2 txclkinv2 txlev2 txbin2 xx x x 1 f igure 9. i llustration of the b ehavior of the tpd ata and t x c lk i nput s gnals , while the t ransmit l ogic b lock is a ccepting s ingle -r ail d ata from the t erminal e quipment txclk tpdata data 1 1 0 ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 32 2.3 t he hdb3/b3zs e ncoder b lock the purpose of the "hdb3/b3zs" encoder block is to aid in the "clock recovery" process (at the remote terminal equipment) by ensuring an upper limit on the number of consecutive zeros that can exist within the line signal. 2.3.1 b3zs encoding if the user has configured the XRT7302 to operate in the ds3 or sonet sts-1 modes, then the "hdb3/ b3zs" encoder blocks will operate in the "b3zs" mode. when the encoder is operating in this mode, it will parse through and search the "transmit binary data stream" (from the transmit logic block) for the occurrence of three (3) consecutive zeros (e.g., "000"). if the "b3zs encoder" finds an occurrence of three consecutive zeros, then it will substitute these three "0s", with either a "00v" or a "b0v" pattern. where: "b" represents a "bipolar" pulse that is compliant with the "alternating polarity" requirements of the ami (al- ternate mark inversion) line code; and "v" represents a "bipolar violation" (e.g., a "bipolar" pulse that violates the "alternating polarity" require- ments of the ami line code). the b3zs encoder will decide whether to substitute with either the "00v" or the "b0v" pattern in order to insure that an odd number of "bipolar" pulses exist between any two consecutive "violation" pulses. figure 10 illustrates the "b3zs encoder" operation, with two separate strings of three (or more) consecu- tive zeros. 2.3.2 hdb3 encoding if the user has configured the XRT7302 to operate in the "e3 mode", then the "hdb3/b3zs" encoder blocks will operate in the "hdb3" mode. when the encoder is operating in this mode, it will parse through and search the "transmit data stream" (from the transmit logic block) for the occurrence of four (4) consecutive zeros (e.g., "0000"). if the "hdb3 en- coder" finds an occurrence of four consecutive zeros, then it will substitute these four "0s", with either a "000v" or a "b00v" pattern. the hdb3 encoder will decide whether to substitute with either the "000v" or the "b00v" pattern in order to insure that an odd num- ber of "bipolar" pulses exist between any two consec- utive "violation" pulses. figure 11 illustrates the "hdb3 encoder" operation, with two separate strings of four (or more) consecu- tive zeros. f igure 10. a n e xample of b3zs e ncoding 1 11000 00 111111111 111 1 0 0 0 0 0 0 0 b0v 00v line signal txclk tndata tpdata data XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 33 2.3.3 disabling the "hdb3/b3zs" encoder the XRT7302 permits the user to disable the "hdb3/ b3zs" encoder by two means. when the XRT7302 is operating in the "hardware" mode. the "hbd3/b3zs encoder" blocks (within both chan- nels) are disabled by setting the "endecdis (encod- er/decoder disable)" input pin (pin 17) to "0". n ote : by executing this step, the user will globally disable the "hdb3/b3zs" encoder and decoder blocks within each channel of the XRT7302. when the XRT7302 is operating in the "host" mode. configuring channel 1 when the XRT7302 is operating in the "host" mode, then the "hdb3/b3zs" encoders (within each chan- nel) can be individually enabled or disabled. the us- er can disable the "hdb3/b3zs encoder" block within channel 1 by setting the "endecdis1" bit-field, with- in command register (cr2), to "1" as illustrated be- low. configuring channel 2 likewise, the user can disable the "hdb3/b3zs en- coder" block within channel 2 by writing a "1" into the "endecdis2" bit-field within command register cr10, as illustrated below. n ote : note: this method can only be used if the XRT7302 is operating in the "host" mode. if the user employs either of these two methods to disable the "hdb3/b3zs" encoder, then the liu will be transmitting the data, onto the line, as it is received via the tpdata and tndata input pins. 2.4 t he t ransmit p ulse s haping c ircuitry the transmit pulse shaper circuitry consists of a transmit line build-out circuit which can be enabled or disabled, by setting the txlev input pin (or "tx- lev" bit-field) to "high" or "low". the purpose of the "transmit line build-out" circuit is to permit the user to configure each channel within the XRT7302 to transmit an output pulse which is compliant to either of the following pulse template requirements (when measured at the digital cross connect system). each of these bellcore specifications further state that the cable length (between the transmit output f igure 11. a n e xample of hdb3 e ncoding 1 11000 00 011111111 110 1 0 0 0 0 0 0 0 b0v 00 v line signal txclk tndata tpdata data 0 0 command register, cr2 (address = 0x02) d4 d3 d2 d1 d0 reserved endecdis1 alosdis1 dlosdis1 reqen1 x 1 xxx command register, cr10 (address = 0x0a) d4 d3 d2 d1 d0 reserved endecdis2 alosdis2 dlosdis2 reqen2 x 1 xxx ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 34 and the digital cross connect system) can range anywhere from 0 to 450 feet. the isolated dsx-3 pulse template requirement (per bellcore gr-499-core) is illustrated in figure 12. the isolated stsx-1 pulse template requirement (per bellcore gr-253-core), is illustrated in figure 13. f igure 12. t he "b ellcore gr-499-core" t ransmit o utput p ulse t emplate for ds3 a pplications ds3 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 tim e , in ui norm alized am plitude lower curve upper curve XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 35 2.4.1 enabling the transmit line build-out cir- cuit if the user enables the "transmit line build-out" cir- cuit, then the "transmit section" of the channel (with- in the XRT7302) will output shaped pulses onto the line via the ttip and tring output pins. the user enables the transmit line build-out circuit (for each channel within the XRT7302) by doing the following: channel 1 in the "hardware" mode ? set the "txlev1" input pin (pin 1) to "low" and; in the "host" mode ? set the "txlev1" bit-field to "0", as illustrated below. channel 2 in the "hardware" mode ? set the "txlev2" input pin (pin 60) to "low". in the "host" mode and; ? set the "txlev2" bit-field to "0", as illustrated below. f igure 13. t he "b ellcore gr-253-core" t ransmit o utput p ulse t emplate for sonet sts-1 a pplications sts-1 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 time, in ui normalized amplitude lower curve upper curve command register, cr1 (address = 0x01) d4 d3 d2 d1 d0 txoff1 taos1 txclkinv1 txlev1 txbin1 0x x 0x ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 36 2.4.2 disabling the transmit line build-out cir- cuit if the user disables the "transmit line build-out" cir- cuit, then the XRT7302 will output un-shaped (e.g., square-wave) pulses onto the line via the ttip and tring output pins. the user disables the transmit line build-out circuit (within the XRT7302) by doing the following: channel 1 in the "hardware" mode. ? set the "txlev1" input pin (pin 1) to "high". and; in the "host" mode. ? set the "txlev1" bit-field to "1" as illustrated below. configuring channel 2 if the XRT7302 is operating in the "hardware" mode. ? set the "txlev2" input pin (pin 60) to "high". and; in the "host" mode. ? set the "txlev2" bit-field to "1", as illustrated below. 2.4.3 design guideline for setting the transmit line build-out circuit the "txlev" input pins or bit-fields should be set based upon the overall cable length between the transmitting terminal and the digital cross connect system (where the pulse template measurements are made). if the cable length (between the transmitting ter- minal and the dsx-3 or stsx-1) is less than 225 feet the user is advised to enable the "transmit line build-out circuit" by setting the "txlev" input pin or bit-field to "0". n ote : in this case, the configured channel (within the XRT7302) will output shaped (e.g., not square-wave) pulses onto the line via its ttip and tring output pins. the shape of this output pulse is such that it will comply with the pulse template requirements even when subjected to cable loss ranging from 0 to 225 feet. if the cable length (between the transmitting ter- minal and the dsx-3 or stsx-1) is greater than 225 feet. the user is advised to disable the "transmit line build-out circuit" by setting the "txlev" input pin or bit-field to "1". n ote : in this case, the configured channel (within the XRT7302) will output un-shaped (e.g., square-wave) pulses onto the line via the ttip and tring output pins. the cable loss, that these pulses will experience over long cable lengths (e.g., greater than 225 feet) will cause these pulses to be "properly shaped" and comply with the appropriate pulse template requirement. 2.4.4 the transmit line build-out circuit and e3 applications the "itu-t g.703 pulse template requirements for e3" states that the e3 transmit output pulse should be measured at the secondary side of the transmit out- put transformer, for "pulse template" compliance. in other words, there is no "digital cross connect sys- tem" pulse template requirement for e3. as a conse- quence, the "transmit line build-out" circuit, within a given channel (within the XRT7302), is disabled whenever that channel has been configured to oper- ate in the e3 mode. 2.5 i nterfacing the t ransmit s ections of the XRT7302 to the l ine the e3, ds3, and sonet sts-1 specification docu- ments all state that line signals transmitted over coax- ial cable are to be terminated with 75 ohm resistor. as a consequence, the user is encouraged to inter- face the "transmit section" of the XRT7302, in the manner as illustrated in figure 14. figure 14 indi- cates that the user should connect two 36 ohm resis- tors in series with the primary side of the transformer. these two 36 ohm resistors will closely match the 75 ohm load termination resistor; thereby maximizing "transmit return loss". command register, cr9 (address = 0x09) d4 d3 d2 d1 d0 txoff2 taos2 txclkinv2 txlev2 txbin2 0x x 0x command register, cr1 (address = 0x01) d4 d3 d2 d1 d0 txoff1 taos1 txclkinv1 txlev1 txbin1 0x x 1x command register, cr9 (address = 0x09) d4 d3 d2 d1 d0 txoff2 taos2 txclkinv2 txlev2 txbin2 0x x 1x XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 37 transformer vendor information pulse corporate office 12220 world trade drive san diego, ca 92128 tel: (619)-674-8100 fax: (619)-674-8262 europe 1 & 2 huxley road the surrey research park guildford, surrey gu2 5re united kingdom f igure 14. r ecommended s chematic for i nterfacing the t ransmit s ection of the XRT7302 to the l ine r1 36 w r2 36 w channel (n) txpos(n) txneg(n) txlineclk(n) ttip(n) tring(n) tpdata(n) tndata(n) txclk(n) only one channel shown 1:1 j1 bnc transmit transformer recommendations p arameter v alue turns ratio 1:1 primary inductance 4h isolation voltage 1500vrms leakage inductance 0.06h p art #i nsulation p ackage t ype pe-68629 3000v large thru-hole pe-65966 1500v small thru-hole pe-65967 1500v small, smt t3001 1500v small, smt p art #i nsulation p ackage t ype ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 38 asia 150 kampong ampat #07-01/02 ka centre singapore 368324 tel: 65-287-8998 fax: 65-280-0080 3.0 the receive section figure 6 indicates that the receive section, within the XRT7302 consists of the following blocks: ? attenuator/equalizer ? peak detector ? slicer ? clock recovery pll ? data recovery ? hdb3/b3zs decoder each of these blocks will be discussed in some detail below. in general, the purpose of the "receive section with- in the XRT7302 is to take an incoming attenuated/dis- torted bipolar signal, from the line, and to encode it back into the ttl/cmos format where it can be re- ceived and processed by the terminal equipment. 3.1 i nterfacing the r eceive s ections of the XRT7302 to the l ine the design of the receive circuitry within the XRT7302 permits the user to transformer-couple or capacitive-couple the receive section to the line. as mentioned earlier, the specification documents for e3, ds3, and sts-1 all specify 75 ohm termination loads, when transmitting over coaxial cable. as a re- sult, it is recommended to interface the "receive sec- tion" of the XRT7302 to the line in a manner as shown in figure 15 and figure 16. f igure 15. r ecommended s chematic for i nterfacing the r eceive s ection of the XRT7302 to the l ine (t ransformer -c oupling ) j1 bnc t1 1:1 r1 37.5 w r2 37.5 w channel (n) rxpos(n) rxneg(n) rxclk(n) rtip(n) rring(n) rpos(n) rneg(n) rxclk(n) c1 0.01uf only one channel shown receive transformer recommendations p arameter v alue turns ratio 1:1 primary inductance 40h isolation voltage 1500vrms leakage inductance 0.6h p art #i nsulation p ackage t ype pe-68629 3000v large thru-hole pe-65966 1500v small thru-hole pe-65967 1500v small, smt t3001 1500v small, smt XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 39 transformer vendor information pulse corporate office 12220 world trade drive san diego, ca 92128 tel: (619)-674-8100 fax: (619)-674-8262 europe 1 & 2 huxley road the surrey research park guildford, surrey gu2 5re united kingdom tel: 44-1483-401700 fax: 44-1483-401701 asia 150 kampong ampat #07-01/02 ka centre singapore 368324 tel: 65-287-8998 fax: 65-280-0080 figure 16 presents the recommended schematic for capacitive-coupling each receive section of the XRT7302 to the line. f igure 16. r ecommended s chematic for i nterfacing the r eceive s ection of the XRT7302 to the l ine (c apacitive -c oupling ) - ( typical channel shown ) r1 75 w j1 bnc channel (n) rxpos(n) rxneg(n) rxclk(n) rtip(n) rring(n) rpos(n) rneg(n) rxclk(n) c1 0.01uf only one channel shown c2 0.01uf ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 40 . 3.2 t he r eceive e qualizer b lock design considerations (for ds3 and sts-1 appli- cations) when installing equipment into environments as de- picted in figure 17, we recommend that the user en- able the receive equalizer, by setting the "reqen1" input pin (for channel 1) or the "reqen2" input pin (for channel 2) high, or the respective bit-fields to "1". in fact, the only time that the user should disable the receive equalizer is when an off-chip equalizer is in the receive path between the digital cross-con- nect system and the rtip/rring input pins, or in ap- plications where the receiver is monitoring the trans- mit output signal directly. design considerations (for e3 applications or if the overall cable length is known) figure 17 indicates the following. a. that the length of cable between the transmitting terminal and the digital cross-connect system can range between 0 and 450 feet. b. that the length of cable between the digital cross- connect system and the receive terminal can range between 0 and 450 feet. as a consequence, the overall cable length (between the transmitting terminal and the receiving terminal) can range between very short cable length (e.g., near 0 feet) up to 900 feet. if, during system installation, the overall cable length is known, then (in order to optimize the performance of the XRT7302, in terms of receive jitter perfor- mance, etc.) the user should enable or disable the receive equalizer, based upon the following recom- mendations. as a guideline, the receive equalizer should be "turned on", if the receive section (of a given chan- nel) is going to receive a line signal with an overall ca- ble length of 300 feet or greater. conversely, the re- f igure 17. i llustration of the t ypical a pplication for the s ystem i nstaller digital cross-connect system transmitting terminal receiving terminal 0 to 450 feet of cable pulses that are compliant to the isolated dsx-3 or stsx-1 pulse template requirement 0 to 450 feet of cable dsx-3 or stsx-1 XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 41 ceive equalizer should be "turned off" if the receive section (of a given channel) is going to receive a line signal over a cable length of less than 300 feet. n otes : 1. if the user turns "on" the receive equalizer block (within a given receive section that is receiving a line signal over short cable length), he/she runs the risks of "over-equalizing" the received line signal which could degrade performance by increasing the amount of jitter that exists within the recovered data and clock signals, or by creating bit-errors. 2. the receive equalizer has been designed to counter the "frequency-dependent" (e.g., cable loss) that a line signal experiences as it travels from the transmitting terminal to the receiving terminal. however, receive equalizer was not designed to counter "flat loss" (e.g., where all of the fourier fre- quency components within the line signal are sub- ject to the same amount of attenuation). flat loss is handled by the agc block. the user can disable the receive equalizer block by doing either of the following. configuring channel 1 1. setting the "reqen1" input pin "low" (when operating in the "hardware" mode); or 2. writing a "0" to the "reqen1" bit-field within command register, cr2 (when operating the XRT7302 in the "host" mode), as illustrated below. configuring channel 2 1. setting the "reqen2" input pin "low" (when operating in the "hardware" mode); or 2. writing a "0" to the "reqen2" bit-field within command register, cr9 (when operating the XRT7302 in the "host" mode), as illustrated below. 3.3 p eak d etector and s licer after the incoming line signal has passed through the receive equalizer block, it will next be routed to the "slicer" block. the purpose of the "slicer" block is to quantify a given bit-period (or symbol) within the in- coming line signal as either a "1" or a "0". 3.4 c lock r ecovery pll the output of the "slicer" block (which is now dual-rail digital pulses) is routed to the clock recovery pll. the purpose of the clock recovery pll is to track the incoming "dual-rail" data stream and to derive and generate a "recovered clock signal". it is important to note that the "clock recovery pll" requires a "line rate" clock signal at the "exclk" input pin. the "clock recovery pll" operates in one of two modes: ? the "training" mode. ? the "data/clock recovery" mode each of these modes will be briefly discussed below. 1. the training mode if a given channel (within the XRT7302) is not receiv- ing a line signal (via the "rtip" and "rring" input pins), or if the frequency difference between the line signal and that applied via the exclk input pin ex- ceeds 0.5%, then the channel will be operating in the "training mode". when the channel is operating in the "training mode", it will do the following: a. declare a "loss of lock" indication, by toggling its respective "rlol" output pin "high". b. output a clock signal (via the rxclk1 and rxclk2 output pins) which is derived from the signal applied to the "exclk" input pin. 2. the "data/clock recovery" mode if the frequency difference between the line signal and that applied via the exclk input pin is less than 0.5%, then the channel will be operating in the "data/ clock recovery" mode. in this mode, the "clock re- command register cr2 (address = 0x02) d4 d3 d2 d1 d0 reserved endecdis1 alosdis1 dlosdis1 reqen1 xxxx 0 command register cr10 (address = 0x0a) d4 d3 d2 d1 d0 reserved endecdis2 alosdis2 dlosdis2 reqen2 xxxx 0 ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 42 covery" pll will be "locked" onto the line signal (via the rtip and rring input pins). 3.5 t he hdb3/b3zs d ecoder the remote transmitting terminal, typically encodes the line signal into some sort of "zero suppression" line code (e.g., hdb3 for e3, and b3zs for ds3 and sts-1). the purpose of this encoding activity was to aid in the clock recovery process, of this data, within the "near-end" receiving terminal. however, once the data has made it across the e3, ds3 or sts-1 transport medium, and has been "recovered" by the clock recovery pll, it is now necessary to restore the original content of the data. hence, the purpose of the "hdb3/b3zs decoding" block is to restore the data (transmitted over the e3, ds3 or sts-1 line) to its original content prior to "zero suppression" cod- ing. 3.5.1 b3zs decoding (ds3/sts-1 applications) if the XRT7302 is configured to operate in the ds3 or sts-1 modes, then the "hdb3/b3zs" decoding blocks will perform "b3zs" decoding. when the de- coders are operating in this mode, each of the decod- ers will parse through its respective incoming "dual rail" data and check for the occurrence of either a "00v" or a "b0v" pattern. if the b3zs decoder de- tects this particular pattern, then it will substitute these bits with a "000" pattern. n ote : if the b3zs decoder detects any bipolar violations that is not in accordance with the"b3zs line code" format; or if the "b3zs decoder" detects a string of 3 (or more) con- secutive "0s", in the incoming line signal, then the "b3zs decoder" will flag this event as a "line code violation" by pulsing the "lcv" output pin "high". figure 18 presents an illustration of the "b3zs de- coder" at work, with two separate "zero suppression" patterns, in the incoming "dual rail data stream". 3.5.2 hdb3 decoding (e3 applications) if the XRT7302 is configured to operate in the "e3 mode" then each of the "hdb3/b3zs" decoding blocks will perform "hdb3" decoding. when the de- coders are operating in this mode, they will each parse through the incoming "dual rail" data and check for the occurrence of either a "000v" or a "b00v" pattern. if the hdb3 decoder detects this particular pattern, then it will substitute these bits with a "0000" pattern. figure 19 presents an illustration of the "hdb3 de- coder" at work, with two separate "zero suppression" patterns, in the incoming "dual rail data stream". f igure 18. a n e xample of b3zs d ecoding line signal rxclk data 1 11000 00 111111111 111 1 0 0 0 0 0 0 0 0 rpos rneg b0v 0v 0 XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 43 n ote : if the hdb3 decoder detects any bipolar violation (e.g., "v") pulses that is not in accordance with the "hdb3 line code" format, or if the "hdb3 decoder" detects a string of 4 (or more) "0's" in the incoming line signal, then the "hdb3 decoder" will flag this event as a "line code violation" by pulsing the "lcv" output pin "high". 3.5.3 configuring the hdb3/b3zs decoder the "hdb3/b3zs decoder" blocks (within each channel of the XRT7302) can be enable or disable by either of the following means. if the XRT7302 is configured to operate in the "host" mode configuring channel 1 the user can enable the "hdb3/b3zs decoder" block within channel 1 by writing a "0" into the "endecdis1" bit-field within command register cr2, as illustrated below. likewise, the user can to disable the "hdb3/b3zs decoder" block within channel 1, by writing a "1" into this bit-field. configuring channel 2 the user can enable the "hdb3/b3zs decoder" block within channel 2 by writing a "0" into the "endecdis2" bit-field within command register cr10, as illustrated below. likewise, the user can to disable the "hdb3/b3zs decoder" block within channel 2 by writing a "1" into this bit-field. if the XRT7302 is configured to operate in the "hardware" mode the user can globally enable both "hdb3/b3zs de- coder" blocks (within the XRT7302) by pulling the "endecdis" input pin "low". conversely, the user can globally disable both "hdb3/b3zs decoder" blocks (within the XRT7302) by pulling the "endec- dis" input pin "high". 3.6 los d eclaration /c learance each channel (within the XRT7302) contains circuitry that will monitor the following two parameters associ- ated with the incoming line signals. 1. the amplitude of the incoming line signal via the rtip and rring inputs; and f igure 19. a n e xample of hdb3 d ecoding b0v 00 v line signal 0 0 rxclk data 1 11000 00 011111111 110 1 0 0 0 0 0 0 0 0 rpos rneg command register cr2 (address = 0x02) d4 d3 d2 d1 d0 rserved endecdis1 alosdis1 dlosdis1 reqen1 x 0xx1 command register cr10 (address = 0x0a) d4 d3 d2 d1 d0 reserved endecdis2 alosdis2 dlosdis2 reqen2 x 0xx1 ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 44 2. the number of pulses, detected (in the incoming line signal) within a certain amount of time. if a given channel (within the XRT7302) determines that the incoming line signal is missing (either due to insufficient amplitude or a lack of pulses in the incom- ing line signal), then it will declare a "loss of signal" (los) condition. the channel (within the XRT7302) declares the los condition by toggling its respective rlos output pin "high", and by setting its corre- sponding "rlos" bit field, within command register 0 (or command register 8) to "1". conversely, if the channel (within the XRT7302) de- termines that the incoming line signal has been re- stored (e.g., there is sufficient amplitude and pulses in the incoming line signal); then it will clear the los condition by toggling its respective rlos output pin "low" and setting its corresponding "rlos" bit-field to "0". in general, the los declaration/clearance scheme that is employed within the XRT7302 is based upon itu-t recommendation g.775 for both e3 and ds3 applications. 3.6.1 the los declaration/clearance criteria for e3 applications when the XRT7302 is operating in the "e3 mode", a given channel will declare an los condition if its "re- ceive line" signal amplitude drops to -35db or below. further, the channel will clear the los condition if its "receive line" signal amplitude rises back up to -15db or above. figure 20 presents an illustration of the sig- nal levels at which each channel (within the XRT7302) will declare and clear los. timing requirements associated with declaring and clearing the los indicator the XRT7302 was designed to meet the itu-t g.775 specification timing requirements for declaring and clearing the los indicator. in particular, a channel (within the XRT7302) will declare an los, between 10 and 255 ui (or e3 bit-periods) after the actual time the los condition occurred. further, the channel will clear the los indicator within 10 to 255 ui after resto- ration of the incoming line signal. figure 21, illus- trates the los declaration and clearance behavior, in response to first, the "loss of signal" event and then afterwards, the restoration of the signal. f igure 20. i llustration of the s ignal l evels that the XRT7302 will declare and clear los 0 db -12 db -15db -35db maximum cable loss for e3 los signal must be declared los signal must be cleared los signal may be cleared or declared XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 45 3.6.2 the los declaration/clearance criteria for ds3 and sts-1 applications when the XRT7302 is operating in the ds3 or sts-1 mode, then each channel (within the XRT7302) will declare and clear los based upon the following two criteria. analog los (alos) declaration/clearance criteria digital los (dlos) declaration/clearance criteria in the ds3 mode, the los output (rlos) is simply the logical "or" of the alos and dlos states. the declaration/clearance criteria for alos and dlos are discussed below. 1. the analog los (alos) declaration/clearance criteria a channel (within the XRT7302) will declare an "ana- log los (alos) condition if the amplitude of the in- coming line signal drops below a specific amplitude as defined by the voltage at the losthr input pin, and by whether the receive equalizer is enabled or not. table 6 presents the various voltage levels at the losthr input pin, the state of the receive equalizer, and the corresponding alos (analog los) threshold amplitudes. f igure 21. t he b ehavior the los o utput i ndicator , in response to the l oss of s ignal , and the r esto - ration of s ignal actual occurrence of los condition line signal is restored time range for los declaration time range for los clearance g.775 g.775 0 ui 10 ui 0 ui 10 ui 255 ui 255 ui rxin rlos output pin t able 6: t he alos (a nalog los) d eclaration and c learance t hresholds for a given setting of losthr and reqen (ds3 and sts-1 a pplications ) a pplication reqen s etting losthr s etting s ignal l evel to d eclare alos s gnal l evel to c lear alos ds3 10< 55mv > 220mv 11< 22mv > 90mv 00< 35mv > 155mv 01< 17mv > 70mv sts-1 10< 75mv > 270mv 11< 25mv > 115mv 00< 55mv > 210mv 01< 20mv > 90mv ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 46 declaring alos a channel (within the XRT7302) will declare alos whenever the amplitude of the receive line signal falls below the "signal level to declare alos" levels specified in table 6. clearing alos a channel (within the XRT7302) will clear alos whenever the amplitude of the receive line signal in- creases above the "signal level to clear alos" lev- els specified in table 6. n ote : there is approximately a 2db hysteresis in the received signal level that exists between declaring and clearing alos, in order to prevent "chattering" in the rlos output signal. monitoring the state of alos if the XRT7302 is operating in the "host" mode, then the user can poll or monitor the state of alos, within channel 1 by reading in the contents of command register 0. the bit-field of command register 0 is presented below. likewise, the user can also poll or monitor the state of alos, within channel 2, by reading in the contents of command register 8. the bit-field of command register 8 is presented below. if the "alos" bit-field contains a "1", then the corre- sponding channel is currently declaring an alos condition. conversely, if the alos bit-field contains a "0", then the channel is not currently declaring an alos condition. disabling the alos detector for debugging purposes, it may be useful to be able to disable the alos detector, within the XRT7302. if the XRT7302 is operating in the "host" mode, then the user can disable the alos detector, (within channel 1) by writing a "1" into the "alosdis1" bit- field, within command register 2; as shown below. likewise, the user can disable the alos detector (within channel 2) by writing a "1" into the "alosdis2" bit-field, within command register 10; as depicted below. 2. the digital los (dlos) declaration/clearance criteria a given channel (within the XRT7302) will declare a digital los (dlos) condition if the XRT7302 detects 16032 or more consecutive "0s" in the incoming da- ta. the channel (within the XRT7302) will clear dlos if it detects four consecutive sets of 32 bit-periods, each command register 0, (address = 0x00) d4 d3 d2 d1 d0 rlol1 rlos1 alos1 dlos1 dmo1 read only read only read only read only read only command register 8, (address = 0x08) d4 d3 d2 d1 d0 rlol2 rlos2 alos2 dlos2 dmo2 read only read only read only read only read only command register cr2 (address = 0x02) d4 d3 d2 d1 d0 reserved endecdis1 alosdis1 dlosdis1 reqen1 xx 1xx command register cr10 (address = 0x0a) d4 d3 d2 d1 d0 reserved endecdis2 alosdis2 dlosdis2 reqen2 xx 1xx XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 47 of which containing at least 10 "1s" (e.g., average pulse density of greater than 33%). monitoring the state of dlos if the XRT7302 is operating in the "host" mode, then the user can poll or monitor the state of dlos, within channel 1 by reading in the contents of command register 0. the bit-field of command register 0 is presented below. likewise, the user can also poll or monitor the state of dlos within channel 2, by reading in the contents of command register 8. the bit-field of command register 8 is presented below. if the dlos bit-field contains a 1, then the corre- sponding channel is currently declaring a dlos con- dition. conversely, if the dlos bit-field contains a 0, then the channel is currently declaring the dlos condition. disabling the dlos detector for debugging purposes, it is useful to be able to dis- able the dlos detector, within the XRT7302. if the XRT7302 is operating in the host mode, the user can disable the dlos detector, (within channel 1) by writing a 1 into the dlosdis1 bit-field, within command register 2, as depicted below. n ote : setting both the "alosdis1" and "dlosdis1" bit- fields to "1" will disable los declaration by channel 1. likewise, the user can disable the dlos detector (within channel 2) by writing a "1" into the "dlosdis2" bit-field, within command register 10, as depicted below. n ote : setting both the "alosdis2" and "dlosdis2" bit- fields to "1" will disable los declaration by channel 2. 3.6.3 muting the recovered data while the los is being declared in some applications it is not desirable for a channel (within the e3/ds3/sts-1 liu) to recover data and route it to the "receiving terminal", while the channel is declaring an los condition. consequently, the XRT7302 includes an "los muting" feature. this feature (if enabled) will cause a given channel (within the XRT7302) to halt transmission of the recovered data (to the receiving terminal) while the los condi- tion is "true". in this case, the rpos and rneg out- put pins will be forced to "0". once the los condition has been cleared, then the channel (within the XRT7302) will resume normal transmission of the re- covered data to the "receiving terminal. this feature is available whenever XRT7302 is oper- ating in the host mode or hardware mode. the ap- proach for configuring the "muting upon los" fea- ture for both the hardware and host modes are pre- sented below. enabling and disabling the "muting upon los" feature if the XRT7302 is operating in the hard- ware mode. to enable the "muting upon los" feature, pull the "losmuten" output pin (pin 53) "high". then, the command register cr0, (address = 0x00) d4 d3 d2 d1 d0 rlol1 rlos1 alos1 dlos1 dmo1 read only read only read only read only read only command register cr8, (address = 0x08) d4 d3 d2 d1 d0 rlol2 rlos2 alos2 dlos2 dmo2 read only read only read only read only read only command register cr2 (address = 0x02 d4 d3 d2 d1 d0 reserved endecdis1 alosdis1 dlosdis1 reqen1 xxx 1x command register cr10 (address = 0x0a d4 d3 d2 d1 d0 reserved endecdis2 alosdis2 dlosdis2 reqen2 xxx 1x ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 48 "muteing upon los" feature will be enabled globally for both channels within the XRT7302. enabling and disabling the "muting upon los" feature if the XRT7302 is operating in the host mode. the "muting upon los" feature for channel 1can be enabled by writing a "1" into the "losmut1" bit-field, within command register 3, as shown below. n otes : 1. this step only enables the "muting upon los" fea- ture within channel 1. 2. each channel, within the XRT7302, automaticallly declares an los (loss of signal) condition any- time it has been configured to operate in either the analog local loop-back or digital local loop- back modes. consequently, the user the user must disable the muting-upon-los feature, prior to configuring the chip to operate in either of these local loop-back modes. the "muting upon los" feature for channel 2 can be enabled by writing a "1" into the "losmut2" bit- field, within command register 11, as shown below. n otes : 1. this step only enables the "muting upon los" fea- ture within channel 1. 2. each channel, within the XRT7302, automaticallly declares an los (loss of signal) condition any- time it has been configured to operate in either the analog local loop-back or digital local loop- back modes. consequently, the user the user must disable the muting-upon-los feature, prior to configuring the chip to operate in either of these local loop-back modes. 3.7 r outing the r ecovered t iming and d ata i nformation to the "r eceiving t erminal e quipment " each channel, within the XRT7302, ultimately takes the recovered timing and data information, converts it into cmos levels and routes it to the receiving ter- minal equipment via the rpos, rneg and rxclk output pins. each channel, within the XRT7302 can "deliver" the recovered data and clock information (to the "receiv- ing terminal") in either a "single-rail" or "dual-rail" format. each of these methods are discussed below. 3.7.1 routing "dual-rail" format data to the receiving terminal equipment whenever a channel (within the XRT7302) delivers dual-rail format to the terminal equipment, it does so via the following signals. ? rpos(n) ? rneg(n) ? rxclk(n) figure 22 presents an illustration of the typical inter- face for the transmission of data in a "dual-rail" for- mat from the receive section of a channel (within the XRT7302) to the "receiving terminal equipment" command register cr3 (address = 0x03) d4 d3 d2 d1 d0 sr/dr _1 losmut1 rxoff1 rclk1_inv reserved x 1x x x command register cr11 (address = 0x0b) d4 d3 d2 d1 d0 sr/dr _2 losmut2 rxoff2 rclk2_inv reserved x 1x x x XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 49 . the manner that a given channel transmits "dual- rail" data (to the receiving terminal equipment) is described below and is illustrated in figure 23. each channel (within the XRT7302) will typically update the data (on the rpos and rneg output pins) on the ris- ing edge rxclk. rxclk, is the recovered clock signal, from the in- coming "received" line signal. as a result, these clock signals are typically 34.368 mhz for e3 applica- tions; 44.736 mhz for ds3 applications, and 51.84 mhz for sonet sts-1 applications. in general, if a given channel (within the XRT7302) received a "positive-polarity" pulse in the incoming line signal (via the rtip and rring input pins), then the channel will pulse its corresponding rpos output pin "high". conversely, if the channel received a "negative-polarity" pulse in the incoming line signal (via the rtip and rring input pins), then the channel will pulse its corresponding rneg output pin "high". inverting the rxclk1 and rxclk2 outputs both channels (within the XRT7302) can invert rx- clk(n) signals, with respect to the "delivery" of the "rpos" and rneg" output signals to the "receiving terminal equipment". this feature may be useful for those customer whose "receiving terminal equip- ment" logic design is such that the rpos and rneg data must be sampled on the rising edge of rxclk. figure 24 illustrates the behavior of the rpos, f igure 22. i llustration of the typical interface for the t ransmission of d ata in a d ual -r ail f ormat , from the "r eceive s ection " of the XRT7302" to the r eceiving t erminal e quipment terminal equipment (e3/ds3 or sts-1 framer) exar e3/ds3/sts-1 liu receive logic block rxpos rxneg rxclk rpos rneg rxclk f igure 23. i llustration on how the XRT7302 outputs data on the rpos and rneg output pins rxclk rpos rneg ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 50 rneg, and rxclk signals, when the rxclk signal has been inverted. inverting the rxclk signals via the host mode in order to configure a single channel (within the XRT7302) to invert the rxclk output signal; the user must be operating the XRT7302 in the "host" mode. if the user wishes to invert rxclk1, associated with channe1, then the user should write a "1" into the "rclk1_inv" bit-field within command register 3. similarly, if the user wishes to invert rxclk2, associ- ated with channel 2, then the user should write a "1" into the "rclk2_inv" bit-field within command regis- ter 11; as illustrated below. inverting the rxclk signals via the hardware mode the user also has the ability to invert both the rxclk1 and rxclk2 output signals while the XRT7302 is op- erating in the "hardware" mode. setting the "rclk- inv" input pin (pin 42) "high" will invert both the rxclk1 and rxclk2 output signals. 3.7.2 routing single-rail format (binary data stream) data to the receive terminal equipment if the user wishes to route "single-rail" format data (e.g., a binary data stream), from the receive section of a channel (within the XRT7302), to the "receiving terminal equipment", he/she can do the following. if the XRT7302 is operating in the "host" mode if the XRT7302 is operating in the "host" mode, then the user has the option to configure each channel (in- dividually) to output data in a single-rail or dual-rail manner to the terminal equipment. a. in order to configure channel 1 to output "single- rail" data to the terminal equipment: write a "1" into the "sr/dr _1" bit-field, within command register 3; as depicted below. b. in order to configure channel 2 to output "single- rail" data to the terminal equipment: write a "1" into the "sr/dr _2" bit-field, within command register 11, as depicted below. after the user has taken these steps, then the config- ured channel (within the XRT7302) will output "sin- gle-rail" data to the "receiving terminal equipment" via its corresponding rpos and rxclk output pins, as illustrated below in figure 25 and figure 26. if the XRT7302 is operating in the hardware mode f igure 24. i llustration of the b ehavior of the rpos, rneg, and r x c lk ( n ) signals , when r x c lk ( n ) is inverted rxclk rpos rneg command register cr3 (address = 0x03) d4 d3 d2 d1 d0 sr/dr _1 losmut1 rxoff1 rclk1_inv reserved xxx 1 x command register cr11 (address = 0x0b) d4 d3 d2 d1 d0 sr/dr _2 losmut2 rxoff2 rclk2_inv reserved xxx 1 x command register cr3 (address = 0x03) d4 d3 d2 d1 d0 sr/dr _1 losmut1 rxoff1 rclk1_inv reserved 1xxx x command register 11 (address = 0x0b) d4 d3 d2 d1 d0 sr/dr _2 losmut2 rxoff2 rclk2_inv reserved 1xx x x XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 51 the user can configure the XRT7302 to output "sin- gle-rail" data from the receive sections of both channels by pulling the "sr/dr " pin (pin 40) to vdd. n ote : when the XRT7302 is operating in the hardware mode, the setting of the "sr/dr " input pin applies to glo- bally to both channels. n ote : the rneg output pin will be internally tied to ground, whenever this feature is implemented. 3.8 s hutting off the r eceive s ection the receive section of each channel of the XRT7302 can be turned off. this feature may be useful in some "redundant system designs". particularly, in those designs where the receive termination within the secondary liu line card, has been "switched-out" and is not receiving any traffic in parallel with the "pri- mary line card". in this case, having the liu (on the "secondary line card) consume the normal amount of current is a waste of power. hence, this feature can permit the user to power down the "receive sec- tion" of the lius on the secondary line card, which will reduce their power consumption by approximately 80%. the user can implement the "rxoff1" by the follow- ing means: if the XRT7302 is operating in the "hardware" mode configuring channel 1 the user can shut off the receive section of channel 1 (within the XRT7302) by pulling the "rxoff1" input pin (pin 19) "high". conversely, the user can turn on the receive section of channel 1 by pulling the "rxoff1" input pin to "low". configuring channel 2 the user can shut off the receive section of channel 2 (within the XRT7302) by pulling the "rxoff2" input pin (pin 18) "high". conversely, the user can turn on the receive section of channel 2 by pulling the "rxoff2" input pin low". if the XRT7302 is operating in the "host" mode configuring channel 1 the user can shut off the receive section of channel 1 (within the XRT7302) by writing a "1" into the f igure 25. i llustration of the typical interface for the t ransmission of d ata in a s ingle -r ail f ormat , from the r eceive s ection of the XRT7302 to the r eceiving t erminal e quipment terminal equipment (e3/ds3 or sts-1 framer) exar e3/ds3/sts-1 liu receive logic block rxpos rxclk rpos rxclk f igure 26. i llustration of the behavior of the rpos and r x c lk output signals , while the XRT7302 is transmitting "s ingle -r ail " data to the r eceiving t erminal e quipment rxclk rpos ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 52 "rxoff1" bit-field (within command register cr3), as illustrated below. conversely, the user can turn on the receive section of channel 1 by writing a "0" into the "rxoff1" bit- field, within command register cr3. configuring channel 2 the user can shut off the receive section of channel 2 (within the XRT7302) by writing a "1" into the "rxoff2" bit-field (within command register, cr11) as illustrated below. conversely, the user can turn on the receive section of channel 2 by writing a "0" into the "rxoff2" bit- field, within command register cr11. command register cr3 (address = 0x03) d4 d3 d2 d1 d0 sr/dr _1 losmut1 rxoff1 rclk1_inv reserved xx 1x x command register cr11 (address = 0x0b) d4 d3 d2 d1 d0 sr/dr _2 losmut2 rxoff2 rclk2_inv reserved xx 1x x XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 53 4.0 diagnostic features of the XRT7302 the XRT7302 supports equipment diagnostic activi- ties by supporting the following loop-back modes within each channel (within the XRT7302). ? analog local loop-back. ? digital local loop-back ? remote loop-back the next two sections briefly discussed each of these loop-back schemes. 4.1 t he a nalog l ocal l oop - back m ode when a given channel (within the XRT7302) is config- ured to operate in the "analog local loop-back" mode, the channel will ignore any signals that are in- put to its rtip and rring input pins. the "transmit- ting terminal equipment" will transmit clock and data into this channel via the tpdata, tndata, and txclk input pins. this data will be processed through the "transmit clock duty cycle circuit" and the "hdb3/ b3zs encoder". finally, this data will be output to the line via the ttip and tring output pins. addition- ally, this data (which is being output via the ttip and tring output pins) will also be looped back into the "receive equalizer block". as a consequence, this data will be processed through the entire "receive section" of the channel. after this "post-loop-back" data has been processed through the "receive sec- tion" it will be output, to the "near-end receiving ter- minal equipment" via the rpos, rneg and rxclk output pins. figure 27 illustrates the path that the data takes (with- in a given channel of the XRT7302), when the chan- nel is configured to operate in the "analog local loop-back" mode. the user can configure a given channel, (within the XRT7302) to operate in the analog local loop-back mode, by employing either one of the following two steps a. if the XRT7302 is operating in the "host" mode to configure channel 1 to operate in the "analog lo- cal loop-back" mode, write a "1" into the "llb1" bit- field and a "0" into the "rlb1" bit-field within com- mand register 4, as illustrated below. f igure 27. i llustration of a t ypical c hannel ( n ) ( within the XRT7302) operating in the a nalog l ocal l oop - back m ode agc/ equalizer peak detector los detector slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr(n) sdi sdo sclk cs regr rtip(n) rring(n) reqen(n) rxclk(n) rpos(n) rneg(n) lcv(n) endecdis rlos(n) llb(n) rlb(n) taos(n) tpdata(n) tndata(n) txclk(n) rlol(n) exclk(n) device monitor mtip(n) mring(n) transmit logic duty cycle adjust txlev(n) txoff(n) dmo(n) ttip(n) tring(n) pulse shaping hdb3/ b3zs encoder serial processor interface analog local loopback path command register cr4 (address = 0x04) d4 d3 d2 d1 d0 x sts-1/ds3 _ch1 e3_ch1 llb1 rlb1 xx x 1 0 ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 54 likewise, to configure channel 2 to operate in the "analog local loop-back" mode, write a "1" into the "llb2" bit-field and a "0" into the "rlb2" bit-field with- in command register 12, as illustrated below. b. if the XRT7302 is operating in the "hardware" mode to configure channel 1 to operate in the "analog lo- cal loop-back" mode, set the "llb1" input pin (pin 24) "high" and the "rlb1" input pin (pin 25) "low". likewise, to configure channel 2 to operate in the "analog local loop-back" mode, set the "llb2" input pin (pin 37) "high" and the "rlb2" input pin (pin 36) "low". n ote : the analog local loop-back mode does not work if the user has turned off the transmitter via the txoff feature. 4.2 t he d igital l ocal l oop - back m ode . when a given channel, within the XRT7302 is config- ured to operate in the "digital local loop-back" mode, the channel will ignore any signals that are in- put to the rtip and rring input pins. the "transmit- ting terminal equipment" will transmit clock and data into the XRT7302 via the "tpdata", "tndata" and "txclk" input pins. this data will be processed through the "transmit clock duty cycle circuit" and the "hdb3/b3zs encoder" block. at this point, this data will be looped back to the "hdb3/b3zs decod- er" block. after this "post-loop back" data has been processed through the "hdb3/b3zs decoder" block, it will be output to the "near-end" receiving terminal equipment" via the rpos, rneg and rxclk output pins. figure 28 illustrates the path that the data takes (with- in the XRT7302), when the chip is configured to oper- ate in the "digital local loop-back" mode. the user can configure a channel (within the XRT7302) to operate in the "digital local loop-back" mode, by employing either one of the following two- steps: a. if the XRT7302 is operating in the "host" mode command register cr12 (address = 0x0c) d4 d3 d2 d1 d0 x sts-1/ds3 _ch2 e3_ch2 llb2 rlb2 xx x 1 0 f igure 28. i llustration of the "d igital l ocal l oop - back " path in a t ypical c hannel ( n ) ( of the XRT7302) agc/ equalizer peak detector los detector slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr(n) sdi sdo sclk cs regr rtip(n) rring(n) reqen(n) rxclk(n) rpos(n) rneg(n) lcv(n) endecdis rlos(n) llb(n) rlb(n) taos(n) tpdata(n) tndata(n) txclk(n) rlol(n) exclk(n) device monitor mtip(n) mring(n) transmit logic duty cycle adjust txlev(n) txoff(n) dmo(n) ttip(n) tring(n) pulse shaping hdb3/ b3zs encoder serial processor interface digital local loopback path XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 55 to configure channel 1 to operate in the "digital local loop-back" mode, write a "1" into both the "llb1" and "rlb1" bit-fields within command register 4, as illustrated below. likewise, configure channel 2 to operate in the "digi- tal local loop-back" mode, write a "1" into both the "llb2" and the "rlb2" bit-fields, within command register 12, as illustrated below. b. if the XRT7302 is operating in the "hardware" mode. to configure channel 1 to operate in the "digital local loop-back" mode, pull both the "llb1" input pin (pin 24) and the "rlb1" input pin (pin 25) "high". likewise, to configure channel 2 to operate in the "digital local loop-back" mode, pull both the "llb2" input pin (pin 37) and the "rlb2" input pin (pin 36) "high". n ote : the digital local loop-back mode will work even if the user has turned off the transmitter via the txoff feature. 4.3 t he r emote l oop - back m ode when a given channel (within the XRT7302) is config- ured to operate in the remote loop-back mode, the channel will ignore any signals that are input to the tpdata and tndata input pins. the channel will re- ceive the incoming line signal, via the rtip and rring input pins. this data will be processed through the entire receive section (within the chan- nel) and will be output to the "receive terminal equipment" via the rpos, rneg and rxclk output pins. additionally, this data will also be internally looped back into the "pulse-shaping" block within the "transmit section". at this point, this data will be rout- ed through the remainder of the "transmit section" of the channel and will be transmitted out onto the line via the ttip and tring output pins. figure 29 illustrates the path that the data takes (with- in the configured channel of the XRT7302), when the chip is configured to operate in the "remote loop- back" mode. command register cr4 (address = 0x04) d4 d3 d2 d1 d0 x sts-1/ds3 _ch1 e3 ch1 llb1 rlb1 xx x 1 1 command register cr12 (address = 0x0c) d4 d3 d2 d1 d0 x sts-1/ds3 _ch2 e3_ch2 llb2 rlb2 xx x 1 1 ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 56 the user can configure a channel (within the XRT7302) to operate in the "remote loop-back" mode, by employing either one of the following two steps a. if the XRT7302 is operating in the "host" mode to configure channel 1 to operate in the "remote loop-back" mode, write a "1" into the "rlb1" bit-field, and a "0" into the "llb1" bit-field, within command register 4, as illustrated below. likewise, to configure channel 2 to operate in the "remote loop-back" mode, write a "1" into the "rlb2" bit-field, and a "0" into the "llb2" bit-field, within command register 12, as illustrated below. b. if the XRT7302 is operating in the "hardware" mode to configure channel 1 to operate in the "remote loop-back" mode, pull both the "rlb1" input pin (pin 25) to "high", and the "llb1" input pin (pin 24) to "low". likewise, to configure channel 2 to operate in the "remote loop-back" mode, pull both the "rlb2" in- put pin (pin 36) to "high", and the "llb2" input pin (pin 37) to "low". 4.4 t x off f eatures the XRT7302 permits the user to shut off the "trans- mit section of each channel (within the XRT7302). when this feature is invoked the transmit section (of the configured channel) will be shut-off, and the transmit output signals (e.g., ttip and tring) will be tri-stated. this feature can come in handy for system redundancy conditions or during diagnostic testing. f igure 29. i llustration of the "r emote l oop - back " path , within a t ypical c hannel ( n ) ( of the XRT7302) agc/ equalizer peak detector los detector slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr(n) sdi sdo sclk cs regr rtip(n) rring(n) reqen(n) rxclk(n) rpos(n) rneg(n) lcv(n) endecdis rlos(n) llb(n) rlb(n) taos(n) tpdata(n) tndata(n) txclk(n) rlol(n) exclk(n) device monitor mtip(n) mring(n) transmit logic duty cycle adjust txlev(n) txoff(n) dmo(n) ttip(n) tring(n) pulse shaping hdb3/ b3zs encoder serial processor interface remote loopback path command register cr4 (address = 0x04) d4 d3 d2 d1 d0 x sts-1/ds3 _ch1 e3_ch1 llb1 rlb1 xx x 0 1 command register cr12 (address = 0x0c) d4 d3 d2 d1 d0 x sts-1/ds3 _ch2 e3_ch2 llb2 rlb2 xx x 0 1 command register cr12 (address = 0x0c) d4 d3 d2 d1 d0 XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 57 the user can activate this feature by either of the fol- lowing ways. when the XRT7302 is operating in the "hardware" mode shutting off the transmitter of channel 1 the user can shut off the transmit driver (within channel 1) by toggling the "txoff1" input pin (pin 80) "high". conversely, the user can turn on the "transmit driver" by toggling the "txoff1" input pin "low". shutting off the transmitter of channel 2 the user can shut off the transmit driver (within channel 2) by toggling the "txoff2" input pin (pin 61) "high". conversely, the user can turn on the "transmit driver" by toggling the "txoff2" input pin "low". when the XRT7302 is operating in the "host" mode shutting off the transmitter of channel 1 the user can turn off the transmit driver (within channel 1) by setting the "txoff1" bit-field (within command register cr1) to "1", as illustrated below. conversely, writing a "0" into this bit-field enables the "transmit driver within channel 1. shutting off the transmitter of channel 2 the user can turn off the transmit driver (within channel 2) by setting the "txoff2" bit-field (within command register cr9) to "1", as illustrated below. conversely, writing a "0" into this bit-field enables the "transmit driver within channel 2. n ote : in order to permit a system (designed for redun- dancy) to quickly shut-off a defective line card and turn-on the back-up line card, the XRT7302 was designed such that either transmitter can quickly be turned-on or turned- off by toggling the txoff1 or txoff2 input pins. this approach is much quicker then setting the txoff1 and txoff2 bit-fields via the microprocessor serial interface. table 7 presents a truth table which relates the set- ting of the txoff external pin and bit-field (for a channel) to the state of the transmitter. please note that this table applies to both channels 1 and 2. as a consequence, if the user wishes to control the state of each transmitter, via the microprocessor seri- al interface, then he/she must connect the txoff1 and txoff2 input pins to gnd. 4.5 t he t ransmit d rive m onitor f eatures the transmit drive monitor permits the user to moni- tor the line, in the transmit direction, for the occur- rence of fault conditions such as a short circuit (on the line), or a defective transmit drive in the XRT7302 or even another liu device. the user activates the transmit drive monitor, within channel 1 by connecting the mtip1 pin (pin 76) to the ttip1 line (through a 270 ohm resistor connect- ed in series); and by connecting the mring1 pin (pin 75) to the tring1 line (through a 270 ohm resistor connected in series). likewise, the user also acti- vates the transmit drive monitor, within channel 2 by connecting the mtip2 pin (pin 65) to the ttip2 line command register cr1 (address = 0x01) d4 d3 d2 d1 d0 txoff1 taos1 txclkinv1 txlev1 txbin1 1xxxx command register cr9 (address = 0x09) d4 d3 d2 d1 d0 txoff2 taos2 txclkinv2 txlev2 txbin2 1xxxx t able 7: t he r elationship b etween the t x off i nput p in , the t x off b it f ield and the s tate of the t ransmitter s tate of the t x off i nput p in s tate of the t x off b it f ield s tate of the t ransmitter low 0 on (transmitter is active) low 1 off (transmitter is tri-stated) high 0 off (transmitter is tri-stated) high 1 off (transmitter is tri-stated) ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 58 (through a 270 ohm resistor connected in series); and by connecting the mring2 pin (pin 66) to the tring2 line (through a 270 ohm resistor connected in series). such an approach is illustrated in figure 30. when the transmit drive monitor circuitry (within a given line) is connected to the line, as illustrated in figure 30, then it will monitor the line for transitions. as long as the transmit drive monitor circuitry de- tects transitions on the line (via the mtip and mring pins), then it will keep the dmo (drive monitor out- put) signal "low". however, if the transmit drive mon- itor circuit detects no transitions on the line for 128(32 txclk periods, then the dmo (drive monitor output) signal will toggle "high". n ote : the user does not have to use the transmit drive monitor circuit in order to operate the transmit section of the XRT7302. this is purely a diagnostic feature. 4.6 t he tao s ( t ransmit a ll o ne s) f eature the XRT7302 permits the user to command either channel to transmit an "all ones" pattern onto the line by toggling a single input pin, or by setting a single bit-field (within one of the command registers) to "1". please note that when this feature is activated, the transmit section of the configured channel (within the XRT7302) will overwrite the "terminal equipment" da- ta with this "all ones" pattern. the user can activate this feature by either of the following ways. when the XRT7302 is operating in the "hardware" mode. configuring channel 1 the user can configure channel 1 (within the XRT7302) to transmit an "all ones" pattern by tog- gling the "taos1" input pin (pin 2) "high". converse- ly, the user can terminate the "all ones" pattern by toggling the "taos1" input pin "low". configuring channel 2 the user can configure channel 2 (within the XRT7302) to transmit an "all ones" pattern by tog- gling the "taos2" input pin (pin 59) "high". con- versely, the user can terminate the "all ones" pattern by toggling the "taos2" input pin "low". when the XRT7302 is operating in the "host" mode. configuring channel 1 the user can configure channel 1 (within the XRT7302) to transmit an "all ones" pattern by writing to command register cr1 and setting the "taos1" bit-field (bit d3) to "1", as illustrated below. conversely, the user can terminate the "all ones" pat- tern by writing to command register, cr1 and set- ting the "taos" bit-field (d3) to "0". configuring channel 2 the user can configure channel 2 (within the XRT7302) to transmit an "all ones" pattern by writing f igure 30. i llustration of a t ypical c hannel of the XRT7302 employing the t ransmit d rive m onitor f eatures r1 = 36 w r2 = 36 w channel (n) txpos(n) txneg(n) txlineclk(n) ttip(n) tring(n) tpdata(n) tndata(n) txclk(n) 1:1 j1 bnc mtip(n) mring(n) r3 = 270 w r4 = 270 w drive_failure (n) dmo(n) command register cr1 (address = 0x01) d4 d3 d2 d1 d0 txoff1 taos1 txclkinv1 txlev1 txbin1 0 1xxx XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 59 to command register cr9 and setting the "taos1" bit-field (bit d3) to "1"; as illustrated below. conversely, the user can terminate the "all ones" pat- tern by writing to command register, cr9 and set- ting the "taos" bit-field (d3) to "0". 5.0 the microprocessor serial inter- face the XRT7302 ds3/e3/sts-1 line interface unit ic permits the user to have access to the "on-chip" command registers. through these command reg- isters, the user can configure the XRT7302 into a wide-variety of modes. this section discusses the following: 1. the description of the command registers. 2. a description on how to use the microprocessor serial interface. 5.1 d escription of the c ommand r egisters table 8 lists the command registers, their address- es, and their bit-formats. command register cr9 (address = 0x09) d4 d3 d2 d1 d0 txoff2 taos2 txclkinv2 txlev2 txbin2 0 1xxx ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 60 the "role/meaning" associated with each of these bit- fields is presented below. address the register addresses presented in the "hexadeci- mal" format. type: the command registers are either "read-only" (ro) type of registers, or are "read/write" (r/w) type of registers. n ote : the default value for each of the bit-fields, within these register will be "0". description of bit-fields for each command reg- ister 5.1.1 command register - cr0 the bit-format and default values for command reg- ister cr0 are listed below. the function of each of these bit-fields are presented below. bit d4 - rlol1 (receive loss of lock status - channel 1) this "read-only" bit-field reflects the "lock" status of the "clock recovery phase-locked-loop", within channel 1 of the XRT7302. this bit-field will be set to "0" if the "clock recovery pll" (within channel 1) is in "lock" with the incoming line signal. conversely, this bit-field will be set to "1" if t able 8: a ddresses and b it f ormats of XRT7302 c ommand r egisters r egister b it -f ormat address command register type d4 d3 d2 d1 d0 0x00 cr0 ro rlol1 rlos1 alos1 dlos1 dmo1 0x01 cr1 r/w txoff1 taos1 txclkinv1 txlev1 txbin1 0x02 cr2 r/w reserved endecdis1 alosdis1 dlosdis1 reqen1 0x03 cr3 r/w sr/dr _1 losmut1 rxoff1 rxclk1_inv reserved 0x04 cr4 r/w reserved sts-1/ds3 _ch1 e3_ch1 llb1 rlb1 0x05 cr5 r/w reserved reserved reserved reserved reserved 0x06 cr6 r/w reserved reserved reserved reserved reserved 0x07 cr7 r/w reserved reserved reserved reserved reserved 0x08 cr8 r/w rlol2 rlos2 alos2 dlos2 dmo2 0x09 cr9 r/w txoff2 taos2 txclkinv2 txlev2 txbin2 0x0a cr10 r/w reserved endecdis2 alosdis2 dlosdis2 reqen2 0x0b cr11 r/w sr/dr _2 losmut2 rxoff2 rxclk2_inv reserved 0x0c cr12 r/w reserved sts-1/ds3 _ch2 e3_ch2 llb2 rlb2 0x0d cr13 r/w reserved reserved reserved reserved reserved 0x0e cr14 r/w reserved reserved reserved reserved reserved 0x0f cr15 r/w reserved reserved reserved reserved reserved command register cr0, (address = 0x00) d4 d3 d2 d1 d0 rlol1 rlos1 alos1 dlos1 dmo1 11111 XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 61 the "clock recovery pll" (within channel 1) is "out of lock" with the incoming line signal. bit d3 - rlos1 (receive loss of signal status - channel 1) this "read-only" bit-field indicates whether or not the receiver, within channel 1 is currently declaring an los (loss of signal) condition. this bit-field will be set to "0" if channel 1 is not (cur- rently) declaring the los condition. conversely, this bit-field will be set to "1" if channel 1 is declaring an los condition. bit d2 - alos1 (analog loss of signal status - channel 1) this "read-only" bit-field indicates whether or not the "analog los detector", within channel 1, is currently declaring an los condition. this bit-field will be set to "0" if the "analog los de- tector", within channel 1, is not (currently) declaring an los condition. conversely, this bit-field will be set to "1" if the "analog los detector", within channel 1, is currently declaring an los condition. n ote : the purpose of this feature is to isolate the detector (e.g., either the "analog los" or the "digital los" detector) that is declaring the los condition. this feature may be useful for troubleshooting/debugging purposes bit d1 - dlos1 (digital loss of signal status - channel 1) this "read-only" bit-field indicates whether or not the "digital los detector", within channel 1, is currently declaring an los condition. this bit-field will be set to "0" if the "digital los de- tector", within channel 1, is not (currently) declaring an los condition. conversely, this bit-field will be set to "1" if the "digital los detector", within channel 1, is currently declaring an los condition. n ote : the purpose of this feature is to isolate the detector (e.g., either the "analog los" or the "digital los" detector) that is declaring the los condition. this feature may be useful for troubleshooting/debugging purposes. bit d0 - dmo1 (drive monitor output status - channel 1) this "read-only" bit-field reflects the status of the dmo1 output pin. 5.1.2 command register cr1 the bit-format and default values for command reg- ister cr1 are listed below. the function of each of these bit-fields are presented below. bit d4 - txoff1 (transmitter off - channel 1) this "read/write" bit-field permits the user to turn off the transmitter (within channel 1). writing a "1" to this bit field will turn off the transmitter and tri-state the transmit output. conversely, writing a "0" to this bit-field will turn-on the transmitter. bit d3 - taos1 (transmit all ones - channel 1) this "read/write" bit-field permits the user to com- mand the transmitter (within channel 1) to generate and transmit an "all ones" pattern onto the line. writing a "1" to this bit-field commands the transmit- ter to transmit an "all ones" pattern onto the line. writing a "0" to this bit-field commands normal opera- tion. bit d2 - txclkinv1 (transmit clock invert - chan- nel 1) this "read/write" bit-field permits the user to config- ure the "transmitter" (within the XRT7302) to sample the signal (at the tpdata and tndata pins) on the "rising edge" or "falling edge" of txclk (the transmit line clock signal). writing a "1" to this bit-field configures the transmitter to sample the tpdata and tndata input pins, on the "rising edge" of txclk. conversely, writing a "0" to this bit-field configures the transmitter to sample the tpdata and tndata input pins, on the "falling edge" of txclk. bit d1 - txlev1 (transmit line build-out enable/ disable select - channel 1) this "read/write" bit-field permits the user to enable or disable the transmit line build-out circuit, within channel 1 of the XRT7302. setting this bit-field "high" disables the line build- out circuit within channel 1. in this mode, channel 1 will output unshaped (e.g., square-wave) pulses onto the line via the ttip1 and tring1 output pins. setting this bit-field "low" enables the line build-out circuit within channel 1. in this mode, channel 1 will output shaped pulses onto the line via the ttip1 and tring1 output pins. command register cr1 (address = 0x01) d4 d3 d2 d1 d0 txoff1 taos1 txclkinv1 txlev1 txbin1 00000 ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 62 in order to comply with the "isolated dsx-3/stsx-1 pulse template requiremnts (per bellcore gr-499- core or gr-253-core), the user should: a. set this bit-field to "1", if the cable length (between the cross-connect and the transmit output of chan- nel 1) is greater than 225 feet. b. set this bit-field to "0", if the cable length (between the cross-connect and the transmit output of chan- nel 1) is less than 225 feet. this bit-field is active only if the XRT7302 is config- ured to operate in the ds3 or sonet sts-1 modes. if the cable length is greater than 225 feet, then the user should set this bit-field to "1" (in order to in- crease the amplitude of the transmit output signal). conversely, if the cable length is less than 225 feet, then the user should set this bit-field to "0". n ote : this option is only available when the XRT7302 is operating in the ds3 or sts-1 mode. bit d0 - txbin1 (transmit binary data - channel 1) this "read/write" bit-field permits the user to config- ure the "transmitter" (within channel 1) to accept an (un-encoded) binary data stream (via the tpdata in- put) and converts this data into the appropriate bipo- lar signal (to the line). writing a "1" configures the "transmitter" to accept a binary data stream via the tpdata input. (note: the tndata input will be ignored). this form of data ac- ceptance is sometimes referred to as "single-rail" mode operation. the transmitter will then encode this data into the appropriate line code (e.g., b3zs or hdb3) prior to its transmission over the line. writing a "0" configures the "transmitter" to accept data in a "dual-rail" manner (e.g., via both the tpdata and tndata inputs). 5.1.3 command register cr2 the bit-format and default values for command reg- ister cr2 are listed below. the function of each of these bit-fields are presented below. bit d4 - reserved bit d3 - endec_dis1 (b3zs/hdb3 encoder/de- coder-disable - channel 1) this "read/write" bit-field permits the user to enable or disable the b3zs/hdb3 encoder and decoder blocks, within channel 1. writing a "1" to this bit-field disables the b3zs/hdb3 encoder and decoder blocks. writing a "0" to this bit- field enables the b3zs/hdb3 encoder and decoder blocks. n ote : this encoder/decoder will perform hdb3 encoding/ decoding if the XRT7302 is operating in the "e3 mode". otherwise, it will perform b3zs encoding/decoding. bit d2 - alosdis1 (analog los disable - channel 1) this "read/write" bit-field permits the user to disable the analog los detector, within channel 1. writing a "0" to this bit-field enables the analog los detector. writing a "1" to this bit-field disables the analog los detector. note: if the user disables the analog los detector, then the rlos input pin will only be asserted by the dlos (digital los detector). bit d1 - dlosdis1 (digital los disable - channel 1) this "read/write" bit-field permits the user to disable the digital los detector within channel 1. writing a "0" to this bit-field enables the digital los detector. writing a "1" to this bit-field disables the digital los detector. n ote : if the user disables the digital los detector, then the rlos input pin will only be asserted by the alos (ana- log los detector). bit d0 - req_en1 (receive equalization enable - channel 1) this "read/write" bit-field permits the user to either enable or disable the internal receive equalizer, with- in channel 1 of the XRT7302. writing a "1" to this bit-field enables the "internal equalizer". conversely, writing a "0" to this bit-field disables the "internal equalizer". 5.1.4 command register cr3 command register cr2 (address = 0x02) d4 d3 d2 d1 d0 reserved endec_dis1 alosdis1 dlosdis1 req_en1 x0000 XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 63 the bit-format and default values for command reg- ister cr3 are listed below. the function of each of these bit-fields are presented below. bit d4 - sr/dr _1 (single-rail/dual-rail data out- put - channel 1) this "read/write" bit-field permits the user to config- ure channel 1 (within the XRT7302) to output the "re- ceived" data (from the remote terminal) in a binary or "dual-rail" format. writing a "1" to this bit-field configures channel 1 to output data (to the terminal equipment) in a binary (single-rail) format via the rpos1 output pin, rneg1 will be grounded. conversely, a "0" to this bit-field configures channel 1 to output data (to the terminal equipment) in a "dual rail" format via both the rpos1 and rneg1 output pins. bit d3 - losmut1 (recovered data muting, dur- ing los condition - channel 1) this "read/write" bit-field permits the user to config- ure channel 1 (within the XRT7302) to not output any recovered data (from the line), while it is declaring an los condition. writing a "0" to this bit-field configures the chip to out- put recovered data, even while the XRT7302 is de- claring an "los" condition. writing a "1" to this bit- field configures the chip to not output the recovered data, while an los condition is being declared. (note: in this mode, rpos1 and rneg1 will be set to "0", asynchronously.) bit d2 - rxoff1 (receive section - shut off se- lect) this "read/write" bit-field permits the user to shut-off the "receive section of channel 1 (within the XRT7302). the purpose of this feature is to permit the user to conserve power consumption when this device is the back-up device in a "redundancy sys- tem". writing a "1" into this bit-field shuts off the receive section of channel 1. conversely, writing a "0" into this bit-field turns on the receive section of channel 1. bit d1 - rxclk1_inv (invert rxclk1) this "read/write" bit-field permits the user to config- ure the "receiver" (within channel 1 of the XRT7302) to output the recovered data on either the "rising edge" or the "falling edge" of the rxclk1 clock signal. writing a "0" to this bit-field configures the receiver to output the recovered data on the "rising edge" of the rxclk1 output signal. writing a "1" to this bit-field configures the receiver to output the recovered data on the "falling edge" of the rxclk1 output signal. bit d0 - reserved this bit-field has no defined functionality command register cr4 the bit-format and default values for command reg- ister cr4 are listed below. the function of each of these bit-fields are presented below. bit d4 - reserved this bit-field has no defined functionality bit d3 - sts-1/ds3 - channel 1 - mode select this "read/write" bit field permits the user to config- ure channel 1, (within the XRT7302) to operate in ei- ther the sonet sts-1 mode or the ds3 mode. writing a "0" into this bit-field configures channel 1 to operate in the "ds3 mode". writing a "1" into this bit- field configures channel 1 to operate in the sonet sts-1 mode. note: this bit-field is ignored if the "e3_ch_1" bit- field (e.g., "d2" within this command register) is set to "1". bit d2 - e3 mode select - channel 1 this "read/write" bit-field permits the user to config- ure channel 1 (within the XRT7302) to operate in the e3 mode. writing a "0" into this bit-field configures channel 1 to operate in either the ds3 or sonet sts-1 mode (as specified by the setting of the "ds3" bit-field within this command register). writing a "1" into this bit- field configures channel 1 to operate in the e3 mode. bit d1 - llb1 (local loop-back - channel 1) command register cr3 (address = 0x03) d4 d3 d2 d1 d0 sr/dr _1 losmut1 rxoff1 rxclk1_inv reserved 0100 0 command register cr4 (address = 0x04) d4 d3 d2 d1 d0 reserved sts-1/ds3 _ch1 e3_ch1 llb1 rlb1 00000 ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 64 this "read/write" bit-field, along with "rlb1" permits the user to configure channel 1 (within the XRT7302) to operate in any one of a variety of loop-back modes. table 9 relates the contents of "llb1" and "rlb1" to the corresponding loop-back mode for channel 1. bit d0 - rlb1 (remote loop-back - channel 1) this "read/write" bit-field, along with "llb1" permits the user to configure channel 1 (within the XRT7302) to operate in any one of a variety of loop-back modes. table 9 relates the contents of "llb1" and "rlb1" to the corresponding loop-back mode for channel 1. 5.1.5 command register - cr8 the bit-format and default values for command reg- ister cr8 are listed below. the function of each of these bit-fields are presented below. bit d4 - rlol2 (receive loss of lock status - channel 2) this "read-only" bit-field reflects the "lock" status of the "clock recovery phase-locked-loop", within channel 2 of the XRT7302. this bit-field will be set to "0" if the "clock recovery pll" (within channel 2) is in "lock" with the incoming line signal. conversely, this bit-field will be set to "1" if the "clock recovery pll" (within channel 2) is "out of lock" with the incoming line signal. bit d3 - rlos2 (receive loss of signal status - channel 2) this "read-only" bit-field indicates whether or not the receiver, within channel 2 is currently declaring an los (loss of signal) condition. this bit-field will be set to "0" if channel 2 is not (cur- rently) declaring the los condition. conversely, this bit-field will be set to "1" if channel 2 is declaring an los condition. bit d2 - alos2 (analog loss of signal status - channel 2) this "read-only" bit-field indicates whether or not the "analog los detector", within channel 2, is currently declaring an los condition. this bit-field will be set to "0" if the "analog los de- tector", within channel 2, is not (currently) declaring an los condition. conversely, this bit-field will be set to "1" if the "analog los detector", within channel 2, is currently declaring an los condition. n ote : the purpose of this feature is to isolate the detector (e.g., either the "analog los" or the "digital los" detector) that is declaring the los condition. this feature may be useful for troubleshooting/debugging purposes. bit d1 - dlos2 (digital loss of signal status - channel 2) this "read-only" bit-field indicates whether or not the "digital los detector", within channel 2, is currently declaring an los condition. this bit-field will be set to "0" if the "digital los de- tector", within channel 2, is not (currently) declaring an los condition. conversely, this bit-field will be set to "1" if the "digital los detector", within channel 2, is currently declaring an los condition. n ote : the purpose of this feature is to isolate the detector (e.g., either the "analog los" or the "digital los" detector) that is declaring the los condition. this feature may be useful for troubleshooting/debugging purposes. bit d0 - dmo2 (drive monitor output status - channel 2) this "read-only" bit-field reflects the status of the dmo2 output pin. 5.1.6 command register cr9 t able 9: c ontents of "llb1" and "rlb1" and the c orresponding l oop -b ack m ode for c hannel 1 llb1 rlb1 l oop -b ack m ode ( for channel 1) 0 0 none 1 0 analog loop-back mode (see section 4.1 for details) 1 1 digital loop-back mode (see section 4.2 for details 0 1 remote loop-back mode (see section 4.3 for details command register 8, (address = 0x08) d4 d3 d2 d1 d0 rlol2 rlos2 alos2 dlos2 dmo2 1 1111 XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 65 the bit-format and default values for command reg- ister cr9 are listed below. the function of each of these bit-fields are presented below. bit d4 - txoff2 (transmitter off - channel 2) this "read/write" bit-field permits the user to turn off the transmitter (within channel 2). writing a "1" to this bit field will turn off the transmitter and tri-state the transmit output. conversely, writing a "0" to this bit-field will turn-on the transmitter. bit d3 - taos2 (transmit all ones - channel 2) this "read/write" bit-field permits the user to com- mand the transmitter (within channel 2) to generate and transmit an "all ones" pattern onto the line. writing a "1" to this bit-field commands the transmit- ter to transmit an "all ones" pattern onto the line. writing a "0" to this bit-field commands normal opera- tion. bit d2 - txclkinv2 (transmit clock invert - chan- nel 2) this "read/write" bit-field permits the user to config- ure the "transmitter" (within the XRT7302) to sample the signal (at the tpdata2 and tndata2 pins) on the "rising edge" or "falling edge" of txclk2 (the transmit line clock signal). writing a "1" to this bit-field configures the transmitter to sample the tpdata2 and tndata2 input pins, on the "rising edge" of txclk2. conversely, writing a "0" to this bit-field configures the transmitter to sample the tpdata2 and tndata2 input pins, on the "falling edge" of txclk2. bit d1 - txlev2 (transmit line build-out enable/ disable select - channel 2) this "read/write" bit-field permits the user to enable or disable the transmit line build-out circuit, within channel 2 of the XRT7302. setting this bit-field "high" disables the line build- out circuit within channel 2. in this mode, channel 2 will output unshaped (e.g., square-wave) pulses onto the line via the ttip2 and tring2 output pins. setting this bit-field "low" enables the line build-out circuit within channel 2. in this mode, channel 2 will output shaped pulses onto the line via the ttip2 and tring2 output pins. in order to comply with the "isolated dsx-3/stsx-1 pulse template requiremnts (per bellcore gr-499- core or gr-253-core), the user should: c. set this bit-field to "1", if the cable length (between the cross-connect and the transmit output of chan- nel 2) is greater than 225 feet. d. set this bit-field to "0", if the cable length (between the cross-connect and the transmit output of chan- nel 2) is less than 225 feet. this bit-field is active only if the XRT7302 is config- ured to operate in the ds3 or sonet sts-1 modes. bit d0 - txbin2 (transmit binary data - channel 2) this "read/write" bit-field permits the user to config- ure the "transmitter" (within channel 2) to accept an (un-encoded) binary data stream (via the tpdata2 in- put) and converts this data into the appropriate bipo- lar signal (to the line). writing a "1" configures the "transmitter" to accept a binary data stream via the tpdata2 input. (note: the tndata2 input will be ignored). this form of data acceptance is sometimes referred to as "single-rail" mode operation. the transmitter will then encode this data into the appropriate line code (e.g., b3zs or hdb3) prior to its transmission over the line. writing a "0" configures the "transmitter" to accept data in a "dual-rail" manner (e.g., via both the tpdata2 and tndata2 inputs). 5.1.7 command register cr10 the bit-format and default values for command reg- ister cr10 are listed below. the function of each of these bit-fields are presented below. bit d4 - reserved this bit-field has no defined functionality command register cr9 (address = 0x09) d4 d3 d2 d1 d0 txoff2 taos2 txclkinv2 txlev2 txbin2 00000 command register cr10 (address = 0x0a) d4 d3 d2 d1 d0 reserved endec_dis2 alosdis2 dlosdis2 req_en2 x0000 ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 66 bit d3 - endec_dis2 (b3zs/hdb3 encoder/de- coder-disable - channel 1) this "read/write" bit-field permits the user to enable or disable the b3zs/hdb3 encoder and decoder blocks, within channel 2. writing a "1" to this bit-field disables the b3zs/hdb3 encoder and decoder blocks. writing a "0" to this bit- field enables the b3zs/hdb3 encoder and decoder blocks. n ote : this encoder/decoder will perform hdb3 encoding/ decoding if the XRT7302 is operating in the "e3 mode". otherwise, it will perform b3zs encoding/decoding. bit d2 - alosdis2 (analog los disable - channel 2) this "read/write" bit-field permits the user to disable the analog los detector, within channel 2. writing a "0" to this bit-field enables the analog los detector. writing a "1" to this bit-field disables the analog los detector. n ote : if the user disables the analog los detector, then the rlos input pin will only be asserted by the dlos (dig- ital los detector). bit d1 - dlosdis2 (digital los disable - channel 2) this "read/write" bit-field permits the user to disable the digital los detector within channel 2. writing a "0" to this bit-field enables the digital los detector. writing a "1" to this bit-field disables the digital los detector. n ote : if the user disables the digital los detector, then the rlos input pin will only be asserted by the alos (ana- log los detector). bit d0 - req_en2 (receive equalization disable - channel 2) this "read/write" bit-field permits the user to either enable or disable the internal receive equalizer (within channel 2). writing a "1" to this bit-field enables the "internal equalizer". conversely, writing a "0" to this bit-field disables the "internal equalizer". 5.2 c ommand r egister cr11 the bit-format and default values for command reg- ister cr11 are listed below. the function of each of these bit-fields are presented below. bit d4 - sr/dr _2 (single-rail/dual-rail data out- put - channel 2) this "read/write" bit-field permits the user to config- ure channel 2 (within the XRT7302) to output the "re- ceived" data (from the remote terminal) in a binary or "dual-rail" format. writing a "1" to this bit-field configures channel 2 to output data (to the terminal equipment) in a binary (single-rail) format via the rpos2 output pin, rneg2 will be grounded. conversely, a "0" to this bit-field configures channel 2 to output data (to the terminal equipment) in a "dual rail" format via both the rpos2 and rneg2 output pins. bit d3 - losmut2 (recovered data muting, dur- ing los condition - channel 2) this "read/write" bit-field permits the user to config- ure channel 2 (within the XRT7302) to not output any recovered data (from the line), while it is declaring an los condition. writing a "0" to this bit-field configures the chip to out- put recovered data, even while the XRT7302 is de- claring an "los" condition. writing a "1" to this bit- field configures the chip to not output the recovered data, while an los condition is being declared. (note: in this mode, rpos2 and rneg2 will be set to "0", asynchronously.) bit d2 - rxoff2 (receive section - shut off se- lect) this "read/write" bit-field permits the user to shut-off the "receive section of channel 2 (within the XRT7302). the purpose of this feature is to permit the user to converse power consumption when this device is the back-up device in a "redundancy sys- tem". writing a "1" into this bit-field shuts off the receive section of channel 2. conversely, writing a "0" into this bit-field turns on the receive section of channel 2. bit d1 - rxclk2_inv (invert rxclk2) this "read/write" bit-field permits the user to config- ure the "receiver" (within channel 2 of the XRT7302) to output the recovered data on either the "rising edge" or the "falling edge" of the rxclk2 clock signal. writing a "0" to this bit-field configures the receiver to output the recovered data on the "rising edge" of the rxclk2 output signal. writing a "1" to this bit-field configures the receiver to output the recovered data on the "falling edge" of the rxclk2 output signal. command register cr11 (address = 0x0b) d4 d3 d2 d1 d0 sr/dr _1 losmut1 rxoff1 rxclk1_inv reserved 0100 0 XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 67 bit d0 - reserved this bit-field has no defined functionality. 5.2.1 command register cr12 the bit-format and default values for command reg- ister cr12 are listed below. the function of each of these bit-fields are presented below. bit d4 - reserved this bit-field has no defined functionality bit d3 - sts-1/ds3 - channel 2 - mode select this "read/write" bit field permits the user to config- ure channel 2, (within the XRT7302) to operate in ei- ther the sonet sts-1 mode or the ds3 mode. writing a "0" into this bit-field configures channel 2 to operate in the "ds3 mode". writing a "1" into this bit- field configures channel 2 to operate in the sonet sts-1 mode. n ote : this bit-field is ignored if the "e3_ch_2" bit-field (e.g., "d2" within this command register) is set to "1". bit d2 - e3 mode select - channel 2 this "read/write" bit-field permits the user to config- ure channel 2 (within the XRT7302) to operate in the e3 mode. writing a "0" into this bit-field configures channel 2 to operate in either the ds3 or sonet sts-1 mode (as specified by the setting of the "ds3" bit-field within this command register). writing a "1" into this bit- field configures channel 2 to operate in the e3 mode. bit d1 - llb2 (local loop-back - channel 2) this "read/write" bit-field, along with "rlb2" permits the user to configure channel 2 (within the XRT7302) to operate in any one of a variety of loop-back modes. table 10 relates the contents of "llb2" and "rlb2" and the corresponding loop-back mode for channel 2. bit d0 - rlb2 (remote loop-back - channel 2) this "read/write" bit-field, along with "llb2" permits the user to configure channel 2 (within the XRT7302) to operate in any one of a variety of loop-back modes. table 10 relates the contents of "llb2" and "rlb2" and the corresponding loop-back mode for channel 2. 5.3 o perating the m icroprocessor s erial i nterface . the XRT7302 serial interface is a simple four wire in- terface that is compatible with many of the microcon- trollers available in the market. this interface con- sists of the following signals: ? cs - chip select (active low) ? sclk - serial clock ? sdi - serial data input ? sdo - serial data output using the microprocessor serial interface the following instructions, for using the microproces- sor serial interface, are best understood by referring to the diagram in figure 31. in order to use the microprocessor serial interface the user must first provide a clock signal to the sclk input pin. afterwards, the user will initiate a "read" or "write" operation by asserting the "active-low" chip select input pin (cs ). it is important to assert the cs pin (e.g., toggle it "low") at least 50ns prior to the very first rising edge of the clock signal. once the cs input pin has been asserted the type of operation and the target register address must now be specified by the user. the user provides this infor- mation to the microprocessor serial interface by writ- ing eight serial bits of data into the sdi input. note: command register cr 12 (address = 0x0c) d4 d3 d2 d1 d0 reserved sts-1/ds3 _ch2 e3_ch2 llb2 rlb2 00000 t able 10: c ontents of "llb2" and "rlb2" and the c orresponding l oop -b ack m ode for c hannel 2 llb2 rlb2 l oop -b ack m ode ( for channel 2) 0 0 none 1 0 analog loop-back mode (see section 4.1 for details) 1 1 digital loop-back mode (see section 4.2 for details 0 1 remote loop-back mode (see section 4.3 for details ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 68 each of these bits will be "clocked" into the sdi input, on the rising edge of sclk. these eight bits are iden- tified and described below. bit 1 - "r/w" (read/write) bit this bit will be clocked into the sdi input, on the first rising edge of sclk (after cs has been asserted). this bit indicates whether the current operation is a "read" or "write" operation. a "1" in this bit specifies a "read" operation; whereas, a "0" in this bit specifies a "write" operation. bits 2 through 5: the four (4) bit address values (labeled a0, a1, a2 and a3) the next four rising edges of the sclk signal will clock in the 4-bit address value for this particular read (or write) operation. the address selects the command register, within the XRT7302 that the user will either be reading data from, or writing data to. the user must supply the address bits to the sdi input pin, in ascending order with the lsb (least significant bit) first. bits 6 and 7: the next two bits, a4 and a5 must be set to "0", as shown in figure 31. bit 8 - a6 the value of "a6" is a "don't care". once these first 8 bits have been written into the mi- croprocessor serial interface, the subsequent action depends upon whether the current operation is a "read" or "write" operation. read operation once the last address bit (a3) has been clocked into the sdi input, the "read" operation will proceed through an idle period, lasting three sclk periods. on the falling edge of sclk cycle #8 (see figure 31) the serial data output signal (sdo) becomes active. at this point the user can begin reading the data con- tents of the addressed command register (at ad- dress [a3, a2, a1, a0]) via the sdo output pin. the microprocessor serial interface will output this five bit data word (d0 through d4) in ascending order (with the lsb first), on the falling edges of the sclk pin. as a consequence, the data (on the sdo output pin) will be sufficiently stable for reading (by the microproces- sor), on the very next rising edge of the sclk pin. write operation once the last address bit (a3) has been clocked into the sdi input, the "write" operation will proceed through an idle period, lasting three sclk periods. prior to the rising edge of sclk cycle # 9 (see figure 31) the user must begin to apply the eight bit data word, that he/she wishes to write to the micro- processor serial interface, onto the sdi input pin. the microprocessor serial interface will latch the val- ue on the sdi input pin, on the rising edge of sclk. the user must apply this word (d0 through d7) serial- ly, in ascending order with the lsb first. simplified interface option the user can simplify the design of the circuitry con- necting to the microprocessor serial interface by ty- ing both the sdo and sdi pins together, and reading data from and/or writing data to this "combined" sig- nal. this simplification is possible because only one of these signals are active at any given time. the in- active signal will be tri-stated. n otes : 1. a4 and a5 are always "0" 2. r/w = "1" for "read" operations 3. r/w = "0" for "write" operations 4. - denotes a "don't care" value f igure 31. m icroprocessor s erial i nterface d ata s tructure d0 d1 d2 0 0 0 d4 d3 high z sdo a0 d0 r/w d1 a6 0 0 a3 a2 a1 d7 d6 d5 d4 d3 d2 sdi 12345678910111213141516 sclk cs high z XRT7302 2 channel e3/ds3/sts-1 line interface unit ? ? ? ? rev. 1.1.5 69 f igure 32. t iming d iagram for the m icroprocessor s erial i nterface sdi r/w a1 a0 cs sclk cs sclk sdi sdo d0 d1 d2 d7 t22 t21 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 hi-z hi-z ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit XRT7302 rev. 1.1.5 70 ordering information package dimensions p art #p ackage o perating temperature r ange XRT7302iv 80 pin thermally enhanced tqfp -40 o c to +85 o c t hermal i nformation theta - j a = 23 c/w theta j c = 5.32 c/w heat slug pure copper ofhc 0.9999 solder plated (package bottom) 80 lead thin quad flat pack with cu heat slug (14x14x1.4mm, tqfp) rev. 1.0 d d 1 d 1 d a 2 a 1 a e b c l a 120 21 40 80 61 60 41 symbol 1.40 1.60 0.055 0.063 a 0.05 0.15 0.002 0.006 a 1 1.35 1.45 0.053 0.057 a 2 8.64 9.40 0.340 0.370 b 0 o 7 o 0 o 7 o a 0.45 0.75 0.018 0.030 l 0.65bsc 0.0256bsc e 13.90 14.10 0.547 0.555 d 1 15.80 16.20 0.622 0.638 d 0.09 0.20 0.004 0.008 c 0.22 0.38 0.009 0.015 b min max min max inches millimeters note: the control dimension is the millimeter column b ? ? ? ? XRT7302 2 channel e3/ds3/sts-1 line interface unit rev. 1.1.5 71 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no represen- tation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys- tem or to significantly affect its safety or effectiveness. products are not authorized for use in such applica- tions unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corpo- ration is adequately protected under the circumstances. copyright 2000 exar corporation datasheet august 2000 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history rev. 1.0.1: pin naming conventions standardized with use of uppercase and lowercase letters. modified and added title to pin out diagram for readability. the pin descriptions for pins 30 (req_en1), 31 (req_en2), 61 (txoff2), 80 (txoff1) have been revised. added table 7. rev. 1.0.2: added absolute maximum ratings and test conditions. book marked pdf file. rev. 1.0.3: minor formatting changes for readability rev. 1.1.0: standardize pin names, updated block diagram, updated electrical characteristics, minor grammar edits, removed preliminary. rev. 1.1.1: pin 7 - receive analog vdd to receive digital vdd and pin 56 - transmit digital gnd instead of receive. nomenclature for gnd and vdd changed to include a-for analog, and d-for digital. package designation from iq to iv. rev. 1.1.2: added tx control title in block diagram. rev. 1.1.3: modified package dimensions drawing adding heat slug integral to package bottom. rev. 1.1.4: modified figures 3 & 4 rev. 1.1.5: modified figure 4, lcv signal |
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